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      1 /*	$NetBSD: intel,agilex5-clkmgr.h,v 1.1.1.1 2026/01/18 05:21:31 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
      4 /*
      5  * Copyright (C) 2023, Intel Corporation
      6  */
      7 
      8 #ifndef __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
      9 #define __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H
     10 
     11 /* fixed rate clocks */
     12 #define AGILEX5_OSC1			0
     13 #define AGILEX5_CB_INTOSC_HS_DIV2_CLK	1
     14 #define AGILEX5_CB_INTOSC_LS_CLK	2
     15 #define AGILEX5_F2S_FREE_CLK		3
     16 
     17 /* PLL clocks */
     18 #define AGILEX5_MAIN_PLL_CLK		4
     19 #define AGILEX5_MAIN_PLL_C0_CLK		5
     20 #define AGILEX5_MAIN_PLL_C1_CLK		6
     21 #define AGILEX5_MAIN_PLL_C2_CLK		7
     22 #define AGILEX5_MAIN_PLL_C3_CLK		8
     23 #define AGILEX5_PERIPH_PLL_CLK		9
     24 #define AGILEX5_PERIPH_PLL_C0_CLK	10
     25 #define AGILEX5_PERIPH_PLL_C1_CLK	11
     26 #define AGILEX5_PERIPH_PLL_C2_CLK	12
     27 #define AGILEX5_PERIPH_PLL_C3_CLK	13
     28 #define AGILEX5_CORE0_FREE_CLK		14
     29 #define AGILEX5_CORE1_FREE_CLK		15
     30 #define AGILEX5_CORE2_FREE_CLK		16
     31 #define AGILEX5_CORE3_FREE_CLK		17
     32 #define AGILEX5_DSU_FREE_CLK		18
     33 #define AGILEX5_BOOT_CLK		19
     34 
     35 /* fixed factor clocks */
     36 #define AGILEX5_L3_MAIN_FREE_CLK	20
     37 #define AGILEX5_NOC_FREE_CLK		21
     38 #define AGILEX5_S2F_USR0_CLK		22
     39 #define AGILEX5_NOC_CLK			23
     40 #define AGILEX5_EMAC_A_FREE_CLK		24
     41 #define AGILEX5_EMAC_B_FREE_CLK		25
     42 #define AGILEX5_EMAC_PTP_FREE_CLK	26
     43 #define AGILEX5_GPIO_DB_FREE_CLK	27
     44 #define AGILEX5_S2F_USER0_FREE_CLK	28
     45 #define AGILEX5_S2F_USER1_FREE_CLK	29
     46 #define AGILEX5_PSI_REF_FREE_CLK	30
     47 #define AGILEX5_USB31_FREE_CLK		31
     48 
     49 /* Gate clocks */
     50 #define AGILEX5_CORE0_CLK		32
     51 #define AGILEX5_CORE1_CLK		33
     52 #define AGILEX5_CORE2_CLK		34
     53 #define AGILEX5_CORE3_CLK		35
     54 #define AGILEX5_MPU_CLK			36
     55 #define AGILEX5_MPU_PERIPH_CLK		37
     56 #define AGILEX5_MPU_CCU_CLK		38
     57 #define AGILEX5_L4_MAIN_CLK		39
     58 #define AGILEX5_L4_MP_CLK		40
     59 #define AGILEX5_L4_SYS_FREE_CLK		41
     60 #define AGILEX5_L4_SP_CLK		42
     61 #define AGILEX5_CS_AT_CLK		43
     62 #define AGILEX5_CS_TRACE_CLK		44
     63 #define AGILEX5_CS_PDBG_CLK		45
     64 #define AGILEX5_EMAC1_CLK		47
     65 #define AGILEX5_EMAC2_CLK		48
     66 #define AGILEX5_EMAC_PTP_CLK		49
     67 #define AGILEX5_GPIO_DB_CLK		50
     68 #define AGILEX5_S2F_USER0_CLK		51
     69 #define AGILEX5_S2F_USER1_CLK		52
     70 #define AGILEX5_PSI_REF_CLK		53
     71 #define AGILEX5_USB31_SUSPEND_CLK	54
     72 #define AGILEX5_EMAC0_CLK		46
     73 #define AGILEX5_USB31_BUS_CLK_EARLY	55
     74 #define AGILEX5_USB2OTG_HCLK		56
     75 #define AGILEX5_SPIM_0_CLK		57
     76 #define AGILEX5_SPIM_1_CLK		58
     77 #define AGILEX5_SPIS_0_CLK		59
     78 #define AGILEX5_SPIS_1_CLK		60
     79 #define AGILEX5_DMA_CORE_CLK		61
     80 #define AGILEX5_DMA_HS_CLK		62
     81 #define AGILEX5_I3C_0_CORE_CLK		63
     82 #define AGILEX5_I3C_1_CORE_CLK		64
     83 #define AGILEX5_I2C_0_PCLK		65
     84 #define AGILEX5_I2C_1_PCLK		66
     85 #define AGILEX5_I2C_EMAC0_PCLK		67
     86 #define AGILEX5_I2C_EMAC1_PCLK		68
     87 #define AGILEX5_I2C_EMAC2_PCLK		69
     88 #define AGILEX5_UART_0_PCLK		70
     89 #define AGILEX5_UART_1_PCLK		71
     90 #define AGILEX5_SPTIMER_0_PCLK		72
     91 #define AGILEX5_SPTIMER_1_PCLK		73
     92 #define AGILEX5_DFI_CLK			74
     93 #define AGILEX5_NAND_NF_CLK		75
     94 #define AGILEX5_NAND_BCH_CLK		76
     95 #define AGILEX5_SDMMC_SDPHY_REG_CLK	77
     96 #define AGILEX5_SDMCLK			78
     97 #define AGILEX5_SOFTPHY_REG_PCLK	79
     98 #define AGILEX5_SOFTPHY_PHY_CLK		80
     99 #define AGILEX5_SOFTPHY_CTRL_CLK	81
    100 #define AGILEX5_NUM_CLKS		82
    101 
    102 #endif	/* __DT_BINDINGS_INTEL_AGILEX5_CLKMGR_H */
    103