1/* $NetBSD: loongson,ls2k-clk.h,v 1.1.1.1 2026/01/18 05:21:31 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Author: Yinbo Zhu <zhuyinbo@loongson.cn> 6 * Copyright (C) 2022-2023 Loongson Technology Corporation Limited 7 */ 8 9#ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H 10#define __DT_BINDINGS_CLOCK_LOONGSON2_H 11 12#define LOONGSON2_REF_100M 0 13#define LOONGSON2_NODE_PLL 1 14#define LOONGSON2_DDR_PLL 2 15#define LOONGSON2_DC_PLL 3 16#define LOONGSON2_PIX0_PLL 4 17#define LOONGSON2_PIX1_PLL 5 18#define LOONGSON2_NODE_CLK 6 19#define LOONGSON2_HDA_CLK 7 20#define LOONGSON2_GPU_CLK 8 21#define LOONGSON2_DDR_CLK 9 22#define LOONGSON2_GMAC_CLK 10 23#define LOONGSON2_DC_CLK 11 24#define LOONGSON2_APB_CLK 12 25#define LOONGSON2_USB_CLK 13 26#define LOONGSON2_SATA_CLK 14 27#define LOONGSON2_PIX0_CLK 15 28#define LOONGSON2_PIX1_CLK 16 29#define LOONGSON2_BOOT_CLK 17 30#define LOONGSON2_OUT0_GATE 18 31#define LOONGSON2_GMAC_GATE 19 32#define LOONGSON2_RIO_GATE 20 33#define LOONGSON2_DC_GATE 21 34#define LOONGSON2_GPU_GATE 22 35#define LOONGSON2_DDR_GATE 23 36#define LOONGSON2_HDA_GATE 24 37#define LOONGSON2_NODE_GATE 25 38#define LOONGSON2_EMMC_GATE 26 39#define LOONGSON2_PIX0_GATE 27 40#define LOONGSON2_PIX1_GATE 28 41#define LOONGSON2_OUT0_CLK 29 42#define LOONGSON2_RIO_CLK 30 43#define LOONGSON2_EMMC_CLK 31 44#define LOONGSON2_DES_CLK 32 45#define LOONGSON2_I2S_CLK 33 46#define LOONGSON2_MISC_CLK 34 47 48#endif 49