1/* $NetBSD: mediatek,mt7981-clk.h,v 1.1.1.1 2026/01/18 05:21:31 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2021 MediaTek Inc. 6 * Author: Wenzhen.Yu <wenzhen.yu@mediatek.com> 7 * Author: Jianhui Zhao <zhaojh329@gmail.com> 8 * Author: Daniel Golle <daniel@makrotopia.org> 9 */ 10 11#ifndef _DT_BINDINGS_CLK_MT7981_H 12#define _DT_BINDINGS_CLK_MT7981_H 13 14/* TOPCKGEN */ 15#define CLK_TOP_CB_CKSQ_40M 0 16#define CLK_TOP_CB_M_416M 1 17#define CLK_TOP_CB_M_D2 2 18#define CLK_TOP_CB_M_D3 3 19#define CLK_TOP_M_D3_D2 4 20#define CLK_TOP_CB_M_D4 5 21#define CLK_TOP_CB_M_D8 6 22#define CLK_TOP_M_D8_D2 7 23#define CLK_TOP_CB_MM_720M 8 24#define CLK_TOP_CB_MM_D2 9 25#define CLK_TOP_CB_MM_D3 10 26#define CLK_TOP_CB_MM_D3_D5 11 27#define CLK_TOP_CB_MM_D4 12 28#define CLK_TOP_CB_MM_D6 13 29#define CLK_TOP_MM_D6_D2 14 30#define CLK_TOP_CB_MM_D8 15 31#define CLK_TOP_CB_APLL2_196M 16 32#define CLK_TOP_APLL2_D2 17 33#define CLK_TOP_APLL2_D4 18 34#define CLK_TOP_NET1_2500M 19 35#define CLK_TOP_CB_NET1_D4 20 36#define CLK_TOP_CB_NET1_D5 21 37#define CLK_TOP_NET1_D5_D2 22 38#define CLK_TOP_NET1_D5_D4 23 39#define CLK_TOP_CB_NET1_D8 24 40#define CLK_TOP_NET1_D8_D2 25 41#define CLK_TOP_NET1_D8_D4 26 42#define CLK_TOP_CB_NET2_800M 27 43#define CLK_TOP_CB_NET2_D2 28 44#define CLK_TOP_CB_NET2_D4 29 45#define CLK_TOP_NET2_D4_D2 30 46#define CLK_TOP_NET2_D4_D4 31 47#define CLK_TOP_CB_NET2_D6 32 48#define CLK_TOP_CB_WEDMCU_208M 33 49#define CLK_TOP_CB_SGM_325M 34 50#define CLK_TOP_CKSQ_40M_D2 35 51#define CLK_TOP_CB_RTC_32K 36 52#define CLK_TOP_CB_RTC_32P7K 37 53#define CLK_TOP_USB_TX250M 38 54#define CLK_TOP_FAUD 39 55#define CLK_TOP_NFI1X 40 56#define CLK_TOP_USB_EQ_RX250M 41 57#define CLK_TOP_USB_CDR_CK 42 58#define CLK_TOP_USB_LN0_CK 43 59#define CLK_TOP_SPINFI_BCK 44 60#define CLK_TOP_SPI 45 61#define CLK_TOP_SPIM_MST 46 62#define CLK_TOP_UART_BCK 47 63#define CLK_TOP_PWM_BCK 48 64#define CLK_TOP_I2C_BCK 49 65#define CLK_TOP_PEXTP_TL 50 66#define CLK_TOP_EMMC_208M 51 67#define CLK_TOP_EMMC_400M 52 68#define CLK_TOP_DRAMC_REF 53 69#define CLK_TOP_DRAMC_MD32 54 70#define CLK_TOP_SYSAXI 55 71#define CLK_TOP_SYSAPB 56 72#define CLK_TOP_ARM_DB_MAIN 57 73#define CLK_TOP_AP2CNN_HOST 58 74#define CLK_TOP_NETSYS 59 75#define CLK_TOP_NETSYS_500M 60 76#define CLK_TOP_NETSYS_WED_MCU 61 77#define CLK_TOP_NETSYS_2X 62 78#define CLK_TOP_SGM_325M 63 79#define CLK_TOP_SGM_REG 64 80#define CLK_TOP_F26M 65 81#define CLK_TOP_EIP97B 66 82#define CLK_TOP_USB3_PHY 67 83#define CLK_TOP_AUD 68 84#define CLK_TOP_A1SYS 69 85#define CLK_TOP_AUD_L 70 86#define CLK_TOP_A_TUNER 71 87#define CLK_TOP_U2U3_REF 72 88#define CLK_TOP_U2U3_SYS 73 89#define CLK_TOP_U2U3_XHCI 74 90#define CLK_TOP_USB_FRMCNT 75 91#define CLK_TOP_NFI1X_SEL 76 92#define CLK_TOP_SPINFI_SEL 77 93#define CLK_TOP_SPI_SEL 78 94#define CLK_TOP_SPIM_MST_SEL 79 95#define CLK_TOP_UART_SEL 80 96#define CLK_TOP_PWM_SEL 81 97#define CLK_TOP_I2C_SEL 82 98#define CLK_TOP_PEXTP_TL_SEL 83 99#define CLK_TOP_EMMC_208M_SEL 84 100#define CLK_TOP_EMMC_400M_SEL 85 101#define CLK_TOP_F26M_SEL 86 102#define CLK_TOP_DRAMC_SEL 87 103#define CLK_TOP_DRAMC_MD32_SEL 88 104#define CLK_TOP_SYSAXI_SEL 89 105#define CLK_TOP_SYSAPB_SEL 90 106#define CLK_TOP_ARM_DB_MAIN_SEL 91 107#define CLK_TOP_AP2CNN_HOST_SEL 92 108#define CLK_TOP_NETSYS_SEL 93 109#define CLK_TOP_NETSYS_500M_SEL 94 110#define CLK_TOP_NETSYS_MCU_SEL 95 111#define CLK_TOP_NETSYS_2X_SEL 96 112#define CLK_TOP_SGM_325M_SEL 97 113#define CLK_TOP_SGM_REG_SEL 98 114#define CLK_TOP_EIP97B_SEL 99 115#define CLK_TOP_USB3_PHY_SEL 100 116#define CLK_TOP_AUD_SEL 101 117#define CLK_TOP_A1SYS_SEL 102 118#define CLK_TOP_AUD_L_SEL 103 119#define CLK_TOP_A_TUNER_SEL 104 120#define CLK_TOP_U2U3_SEL 105 121#define CLK_TOP_U2U3_SYS_SEL 106 122#define CLK_TOP_U2U3_XHCI_SEL 107 123#define CLK_TOP_USB_FRMCNT_SEL 108 124#define CLK_TOP_AUD_I2S_M 109 125 126/* INFRACFG */ 127#define CLK_INFRA_66M_MCK 0 128#define CLK_INFRA_UART0_SEL 1 129#define CLK_INFRA_UART1_SEL 2 130#define CLK_INFRA_UART2_SEL 3 131#define CLK_INFRA_SPI0_SEL 4 132#define CLK_INFRA_SPI1_SEL 5 133#define CLK_INFRA_SPI2_SEL 6 134#define CLK_INFRA_PWM1_SEL 7 135#define CLK_INFRA_PWM2_SEL 8 136#define CLK_INFRA_PWM3_SEL 9 137#define CLK_INFRA_PWM_BSEL 10 138#define CLK_INFRA_PCIE_SEL 11 139#define CLK_INFRA_GPT_STA 12 140#define CLK_INFRA_PWM_HCK 13 141#define CLK_INFRA_PWM_STA 14 142#define CLK_INFRA_PWM1_CK 15 143#define CLK_INFRA_PWM2_CK 16 144#define CLK_INFRA_PWM3_CK 17 145#define CLK_INFRA_CQ_DMA_CK 18 146#define CLK_INFRA_AUD_BUS_CK 19 147#define CLK_INFRA_AUD_26M_CK 20 148#define CLK_INFRA_AUD_L_CK 21 149#define CLK_INFRA_AUD_AUD_CK 22 150#define CLK_INFRA_AUD_EG2_CK 23 151#define CLK_INFRA_DRAMC_26M_CK 24 152#define CLK_INFRA_DBG_CK 25 153#define CLK_INFRA_AP_DMA_CK 26 154#define CLK_INFRA_SEJ_CK 27 155#define CLK_INFRA_SEJ_13M_CK 28 156#define CLK_INFRA_THERM_CK 29 157#define CLK_INFRA_I2C0_CK 30 158#define CLK_INFRA_UART0_CK 31 159#define CLK_INFRA_UART1_CK 32 160#define CLK_INFRA_UART2_CK 33 161#define CLK_INFRA_SPI2_CK 34 162#define CLK_INFRA_SPI2_HCK_CK 35 163#define CLK_INFRA_NFI1_CK 36 164#define CLK_INFRA_SPINFI1_CK 37 165#define CLK_INFRA_NFI_HCK_CK 38 166#define CLK_INFRA_SPI0_CK 39 167#define CLK_INFRA_SPI1_CK 40 168#define CLK_INFRA_SPI0_HCK_CK 41 169#define CLK_INFRA_SPI1_HCK_CK 42 170#define CLK_INFRA_FRTC_CK 43 171#define CLK_INFRA_MSDC_CK 44 172#define CLK_INFRA_MSDC_HCK_CK 45 173#define CLK_INFRA_MSDC_133M_CK 46 174#define CLK_INFRA_MSDC_66M_CK 47 175#define CLK_INFRA_ADC_26M_CK 48 176#define CLK_INFRA_ADC_FRC_CK 49 177#define CLK_INFRA_FBIST2FPC_CK 50 178#define CLK_INFRA_I2C_MCK_CK 51 179#define CLK_INFRA_I2C_PCK_CK 52 180#define CLK_INFRA_IUSB_133_CK 53 181#define CLK_INFRA_IUSB_66M_CK 54 182#define CLK_INFRA_IUSB_SYS_CK 55 183#define CLK_INFRA_IUSB_CK 56 184#define CLK_INFRA_IPCIE_CK 57 185#define CLK_INFRA_IPCIE_PIPE_CK 58 186#define CLK_INFRA_IPCIER_CK 59 187#define CLK_INFRA_IPCIEB_CK 60 188 189/* APMIXEDSYS */ 190#define CLK_APMIXED_ARMPLL 0 191#define CLK_APMIXED_NET2PLL 1 192#define CLK_APMIXED_MMPLL 2 193#define CLK_APMIXED_SGMPLL 3 194#define CLK_APMIXED_WEDMCUPLL 4 195#define CLK_APMIXED_NET1PLL 5 196#define CLK_APMIXED_MPLL 6 197#define CLK_APMIXED_APLL2 7 198 199/* SGMIISYS_0 */ 200#define CLK_SGM0_TX_EN 0 201#define CLK_SGM0_RX_EN 1 202#define CLK_SGM0_CK0_EN 2 203#define CLK_SGM0_CDR_CK0_EN 3 204 205/* SGMIISYS_1 */ 206#define CLK_SGM1_TX_EN 0 207#define CLK_SGM1_RX_EN 1 208#define CLK_SGM1_CK1_EN 2 209#define CLK_SGM1_CDR_CK1_EN 3 210 211/* ETHSYS */ 212#define CLK_ETH_FE_EN 0 213#define CLK_ETH_GP2_EN 1 214#define CLK_ETH_GP1_EN 2 215#define CLK_ETH_WOCPU0_EN 3 216 217#endif /* _DT_BINDINGS_CLK_MT7981_H */ 218