1 /* $NetBSD: mediatek,mt6795-clk.h,v 1.1.1.1 2026/01/18 05:21:31 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) */ 4 /* 5 * Copyright (c) 2022 Collabora Ltd. 6 * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno (at) collabora.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_MT6795_H 10 #define _DT_BINDINGS_CLK_MT6795_H 11 12 /* TOPCKGEN */ 13 #define CLK_TOP_ADSYS_26M 0 14 #define CLK_TOP_CLKPH_MCK_O 1 15 #define CLK_TOP_USB_SYSPLL_125M 2 16 #define CLK_TOP_DSI0_DIG 3 17 #define CLK_TOP_DSI1_DIG 4 18 #define CLK_TOP_ARMCA53PLL_754M 5 19 #define CLK_TOP_ARMCA53PLL_502M 6 20 #define CLK_TOP_MAIN_H546M 7 21 #define CLK_TOP_MAIN_H364M 8 22 #define CLK_TOP_MAIN_H218P4M 9 23 #define CLK_TOP_MAIN_H156M 10 24 #define CLK_TOP_TVDPLL_445P5M 11 25 #define CLK_TOP_TVDPLL_594M 12 26 #define CLK_TOP_UNIV_624M 13 27 #define CLK_TOP_UNIV_416M 14 28 #define CLK_TOP_UNIV_249P6M 15 29 #define CLK_TOP_UNIV_178P3M 16 30 #define CLK_TOP_UNIV_48M 17 31 #define CLK_TOP_CLKRTC_EXT 18 32 #define CLK_TOP_CLKRTC_INT 19 33 #define CLK_TOP_FPC 20 34 #define CLK_TOP_HDMITXPLL_D2 21 35 #define CLK_TOP_HDMITXPLL_D3 22 36 #define CLK_TOP_ARMCA53PLL_D2 23 37 #define CLK_TOP_ARMCA53PLL_D3 24 38 #define CLK_TOP_APLL1 25 39 #define CLK_TOP_APLL2 26 40 #define CLK_TOP_DMPLL 27 41 #define CLK_TOP_DMPLL_D2 28 42 #define CLK_TOP_DMPLL_D4 29 43 #define CLK_TOP_DMPLL_D8 30 44 #define CLK_TOP_DMPLL_D16 31 45 #define CLK_TOP_MMPLL 32 46 #define CLK_TOP_MMPLL_D2 33 47 #define CLK_TOP_MSDCPLL 34 48 #define CLK_TOP_MSDCPLL_D2 35 49 #define CLK_TOP_MSDCPLL_D4 36 50 #define CLK_TOP_MSDCPLL2 37 51 #define CLK_TOP_MSDCPLL2_D2 38 52 #define CLK_TOP_MSDCPLL2_D4 39 53 #define CLK_TOP_SYSPLL_D2 40 54 #define CLK_TOP_SYSPLL1_D2 41 55 #define CLK_TOP_SYSPLL1_D4 42 56 #define CLK_TOP_SYSPLL1_D8 43 57 #define CLK_TOP_SYSPLL1_D16 44 58 #define CLK_TOP_SYSPLL_D3 45 59 #define CLK_TOP_SYSPLL2_D2 46 60 #define CLK_TOP_SYSPLL2_D4 47 61 #define CLK_TOP_SYSPLL_D5 48 62 #define CLK_TOP_SYSPLL3_D2 49 63 #define CLK_TOP_SYSPLL3_D4 50 64 #define CLK_TOP_SYSPLL_D7 51 65 #define CLK_TOP_SYSPLL4_D2 52 66 #define CLK_TOP_SYSPLL4_D4 53 67 #define CLK_TOP_TVDPLL 54 68 #define CLK_TOP_TVDPLL_D2 55 69 #define CLK_TOP_TVDPLL_D4 56 70 #define CLK_TOP_TVDPLL_D8 57 71 #define CLK_TOP_TVDPLL_D16 58 72 #define CLK_TOP_UNIVPLL_D2 59 73 #define CLK_TOP_UNIVPLL1_D2 60 74 #define CLK_TOP_UNIVPLL1_D4 61 75 #define CLK_TOP_UNIVPLL1_D8 62 76 #define CLK_TOP_UNIVPLL_D3 63 77 #define CLK_TOP_UNIVPLL2_D2 64 78 #define CLK_TOP_UNIVPLL2_D4 65 79 #define CLK_TOP_UNIVPLL2_D8 66 80 #define CLK_TOP_UNIVPLL_D5 67 81 #define CLK_TOP_UNIVPLL3_D2 68 82 #define CLK_TOP_UNIVPLL3_D4 69 83 #define CLK_TOP_UNIVPLL3_D8 70 84 #define CLK_TOP_UNIVPLL_D7 71 85 #define CLK_TOP_UNIVPLL_D26 72 86 #define CLK_TOP_UNIVPLL_D52 73 87 #define CLK_TOP_VCODECPLL 74 88 #define CLK_TOP_VCODECPLL_370P5 75 89 #define CLK_TOP_VENCPLL 76 90 #define CLK_TOP_VENCPLL_D2 77 91 #define CLK_TOP_VENCPLL_D4 78 92 #define CLK_TOP_AXI_SEL 79 93 #define CLK_TOP_MEM_SEL 80 94 #define CLK_TOP_DDRPHYCFG_SEL 81 95 #define CLK_TOP_MM_SEL 82 96 #define CLK_TOP_PWM_SEL 83 97 #define CLK_TOP_VDEC_SEL 84 98 #define CLK_TOP_VENC_SEL 85 99 #define CLK_TOP_MFG_SEL 86 100 #define CLK_TOP_CAMTG_SEL 87 101 #define CLK_TOP_UART_SEL 88 102 #define CLK_TOP_SPI_SEL 89 103 #define CLK_TOP_USB20_SEL 90 104 #define CLK_TOP_USB30_SEL 91 105 #define CLK_TOP_MSDC50_0_H_SEL 92 106 #define CLK_TOP_MSDC50_0_SEL 93 107 #define CLK_TOP_MSDC30_1_SEL 94 108 #define CLK_TOP_MSDC30_2_SEL 95 109 #define CLK_TOP_MSDC30_3_SEL 96 110 #define CLK_TOP_AUDIO_SEL 97 111 #define CLK_TOP_AUD_INTBUS_SEL 98 112 #define CLK_TOP_PMICSPI_SEL 99 113 #define CLK_TOP_SCP_SEL 100 114 #define CLK_TOP_MJC_SEL 101 115 #define CLK_TOP_DPI0_SEL 102 116 #define CLK_TOP_IRDA_SEL 103 117 #define CLK_TOP_CCI400_SEL 104 118 #define CLK_TOP_AUD_1_SEL 105 119 #define CLK_TOP_AUD_2_SEL 106 120 #define CLK_TOP_MEM_MFG_IN_SEL 107 121 #define CLK_TOP_AXI_MFG_IN_SEL 108 122 #define CLK_TOP_SCAM_SEL 109 123 #define CLK_TOP_I2S0_M_SEL 110 124 #define CLK_TOP_I2S1_M_SEL 111 125 #define CLK_TOP_I2S2_M_SEL 112 126 #define CLK_TOP_I2S3_M_SEL 113 127 #define CLK_TOP_I2S3_B_SEL 114 128 #define CLK_TOP_APLL1_DIV0 115 129 #define CLK_TOP_APLL1_DIV1 116 130 #define CLK_TOP_APLL1_DIV2 117 131 #define CLK_TOP_APLL1_DIV3 118 132 #define CLK_TOP_APLL1_DIV4 119 133 #define CLK_TOP_APLL1_DIV5 120 134 #define CLK_TOP_APLL2_DIV0 121 135 #define CLK_TOP_APLL2_DIV1 122 136 #define CLK_TOP_APLL2_DIV2 123 137 #define CLK_TOP_APLL2_DIV3 124 138 #define CLK_TOP_APLL2_DIV4 125 139 #define CLK_TOP_APLL2_DIV5 126 140 #define CLK_TOP_NR_CLK 127 141 142 /* APMIXED_SYS */ 143 #define CLK_APMIXED_ARMCA53PLL 0 144 #define CLK_APMIXED_MAINPLL 1 145 #define CLK_APMIXED_UNIVPLL 2 146 #define CLK_APMIXED_MMPLL 3 147 #define CLK_APMIXED_MSDCPLL 4 148 #define CLK_APMIXED_VENCPLL 5 149 #define CLK_APMIXED_TVDPLL 6 150 #define CLK_APMIXED_MPLL 7 151 #define CLK_APMIXED_VCODECPLL 8 152 #define CLK_APMIXED_APLL1 9 153 #define CLK_APMIXED_APLL2 10 154 #define CLK_APMIXED_REF2USB_TX 11 155 #define CLK_APMIXED_NR_CLK 12 156 157 /* INFRA_SYS */ 158 #define CLK_INFRA_DBGCLK 0 159 #define CLK_INFRA_SMI 1 160 #define CLK_INFRA_AUDIO 2 161 #define CLK_INFRA_GCE 3 162 #define CLK_INFRA_L2C_SRAM 4 163 #define CLK_INFRA_M4U 5 164 #define CLK_INFRA_MD1MCU 6 165 #define CLK_INFRA_MD1BUS 7 166 #define CLK_INFRA_MD1DBB 8 167 #define CLK_INFRA_DEVICE_APC 9 168 #define CLK_INFRA_TRNG 10 169 #define CLK_INFRA_MD1LTE 11 170 #define CLK_INFRA_CPUM 12 171 #define CLK_INFRA_KP 13 172 #define CLK_INFRA_CA53_C0_SEL 14 173 #define CLK_INFRA_CA53_C1_SEL 15 174 #define CLK_INFRA_NR_CLK 16 175 176 /* PERI_SYS */ 177 #define CLK_PERI_NFI 0 178 #define CLK_PERI_THERM 1 179 #define CLK_PERI_PWM1 2 180 #define CLK_PERI_PWM2 3 181 #define CLK_PERI_PWM3 4 182 #define CLK_PERI_PWM4 5 183 #define CLK_PERI_PWM5 6 184 #define CLK_PERI_PWM6 7 185 #define CLK_PERI_PWM7 8 186 #define CLK_PERI_PWM 9 187 #define CLK_PERI_USB0 10 188 #define CLK_PERI_USB1 11 189 #define CLK_PERI_AP_DMA 12 190 #define CLK_PERI_MSDC30_0 13 191 #define CLK_PERI_MSDC30_1 14 192 #define CLK_PERI_MSDC30_2 15 193 #define CLK_PERI_MSDC30_3 16 194 #define CLK_PERI_NLI_ARB 17 195 #define CLK_PERI_IRDA 18 196 #define CLK_PERI_UART0 19 197 #define CLK_PERI_UART1 20 198 #define CLK_PERI_UART2 21 199 #define CLK_PERI_UART3 22 200 #define CLK_PERI_I2C0 23 201 #define CLK_PERI_I2C1 24 202 #define CLK_PERI_I2C2 25 203 #define CLK_PERI_I2C3 26 204 #define CLK_PERI_I2C4 27 205 #define CLK_PERI_AUXADC 28 206 #define CLK_PERI_SPI0 29 207 #define CLK_PERI_UART0_SEL 30 208 #define CLK_PERI_UART1_SEL 31 209 #define CLK_PERI_UART2_SEL 32 210 #define CLK_PERI_UART3_SEL 33 211 #define CLK_PERI_NR_CLK 34 212 213 /* MFG */ 214 #define CLK_MFG_BAXI 0 215 #define CLK_MFG_BMEM 1 216 #define CLK_MFG_BG3D 2 217 #define CLK_MFG_B26M 3 218 #define CLK_MFG_NR_CLK 4 219 220 /* MM_SYS */ 221 #define CLK_MM_SMI_COMMON 0 222 #define CLK_MM_SMI_LARB0 1 223 #define CLK_MM_CAM_MDP 2 224 #define CLK_MM_MDP_RDMA0 3 225 #define CLK_MM_MDP_RDMA1 4 226 #define CLK_MM_MDP_RSZ0 5 227 #define CLK_MM_MDP_RSZ1 6 228 #define CLK_MM_MDP_RSZ2 7 229 #define CLK_MM_MDP_TDSHP0 8 230 #define CLK_MM_MDP_TDSHP1 9 231 #define CLK_MM_MDP_CROP 10 232 #define CLK_MM_MDP_WDMA 11 233 #define CLK_MM_MDP_WROT0 12 234 #define CLK_MM_MDP_WROT1 13 235 #define CLK_MM_FAKE_ENG 14 236 #define CLK_MM_MUTEX_32K 15 237 #define CLK_MM_DISP_OVL0 16 238 #define CLK_MM_DISP_OVL1 17 239 #define CLK_MM_DISP_RDMA0 18 240 #define CLK_MM_DISP_RDMA1 19 241 #define CLK_MM_DISP_RDMA2 20 242 #define CLK_MM_DISP_WDMA0 21 243 #define CLK_MM_DISP_WDMA1 22 244 #define CLK_MM_DISP_COLOR0 23 245 #define CLK_MM_DISP_COLOR1 24 246 #define CLK_MM_DISP_AAL 25 247 #define CLK_MM_DISP_GAMMA 26 248 #define CLK_MM_DISP_UFOE 27 249 #define CLK_MM_DISP_SPLIT0 28 250 #define CLK_MM_DISP_SPLIT1 29 251 #define CLK_MM_DISP_MERGE 30 252 #define CLK_MM_DISP_OD 31 253 #define CLK_MM_DISP_PWM0MM 32 254 #define CLK_MM_DISP_PWM026M 33 255 #define CLK_MM_DISP_PWM1MM 34 256 #define CLK_MM_DISP_PWM126M 35 257 #define CLK_MM_DSI0_ENGINE 36 258 #define CLK_MM_DSI0_DIGITAL 37 259 #define CLK_MM_DSI1_ENGINE 38 260 #define CLK_MM_DSI1_DIGITAL 39 261 #define CLK_MM_DPI_PIXEL 40 262 #define CLK_MM_DPI_ENGINE 41 263 #define CLK_MM_NR_CLK 42 264 265 /* VDEC_SYS */ 266 #define CLK_VDEC_CKEN 0 267 #define CLK_VDEC_LARB_CKEN 1 268 #define CLK_VDEC_NR_CLK 2 269 270 /* VENC_SYS */ 271 #define CLK_VENC_LARB 0 272 #define CLK_VENC_VENC 1 273 #define CLK_VENC_JPGENC 2 274 #define CLK_VENC_JPGDEC 3 275 #define CLK_VENC_NR_CLK 4 276 277 #endif /* _DT_BINDINGS_CLK_MT6795_H */ 278
Indexes created Thu Apr 30 00:23:01 UTC 2026