1/*	$NetBSD: microchip,mpfs-clock.h,v 1.1 2024/08/12 10:55:56 skrll Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
4/*
5 * Daire McNamara,<daire.mcnamara@microchip.com>
6 * Copyright (C) 2020-2022 Microchip Technology Inc.  All rights reserved.
7 */
8
9#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
10#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
11
12#define CLK_CPU		0
13#define CLK_AXI		1
14#define CLK_AHB		2
15
16#define CLK_ENVM	3
17#define CLK_MAC0	4
18#define CLK_MAC1	5
19#define CLK_MMC		6
20#define CLK_TIMER	7
21#define CLK_MMUART0	8
22#define CLK_MMUART1	9
23#define CLK_MMUART2	10
24#define CLK_MMUART3	11
25#define CLK_MMUART4	12
26#define CLK_SPI0	13
27#define CLK_SPI1	14
28#define CLK_I2C0	15
29#define CLK_I2C1	16
30#define CLK_CAN0	17
31#define CLK_CAN1	18
32#define CLK_USB		19
33#define CLK_RESERVED	20
34#define CLK_RTC		21
35#define CLK_QSPI	22
36#define CLK_GPIO0	23
37#define CLK_GPIO1	24
38#define CLK_GPIO2	25
39#define CLK_DDRC	26
40#define CLK_FIC0	27
41#define CLK_FIC1	28
42#define CLK_FIC2	29
43#define CLK_FIC3	30
44#define CLK_ATHENA	31
45#define CLK_CFM		32
46
47#define CLK_RTCREF	33
48#define CLK_MSSPLL	34
49#define CLK_MSSPLL0	34
50#define CLK_MSSPLL1	35
51#define CLK_MSSPLL2	36
52#define CLK_MSSPLL3	37
53/* 38 is reserved for MSS PLL internals */
54
55/* Clock Conditioning Circuitry Clock IDs */
56
57#define CLK_CCC_PLL0		0
58#define CLK_CCC_PLL1		1
59#define CLK_CCC_DLL0		2
60#define CLK_CCC_DLL1		3
61
62#define CLK_CCC_PLL0_OUT0	4
63#define CLK_CCC_PLL0_OUT1	5
64#define CLK_CCC_PLL0_OUT2	6
65#define CLK_CCC_PLL0_OUT3	7
66
67#define CLK_CCC_PLL1_OUT0	8
68#define CLK_CCC_PLL1_OUT1	9
69#define CLK_CCC_PLL1_OUT2	10
70#define CLK_CCC_PLL1_OUT3	11
71
72#define CLK_CCC_DLL0_OUT0	12
73#define CLK_CCC_DLL0_OUT1	13
74
75#define CLK_CCC_DLL1_OUT0	14
76#define CLK_CCC_DLL1_OUT1	15
77
78#endif	/* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
79