1 /* $NetBSD: mt8183-clk.h,v 1.1.1.1 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2018 MediaTek Inc. 6 * Author: Weiyi Lu <weiyi.lu (at) mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_MT8183_H 10 #define _DT_BINDINGS_CLK_MT8183_H 11 12 /* APMIXED */ 13 #define CLK_APMIXED_ARMPLL_LL 0 14 #define CLK_APMIXED_ARMPLL_L 1 15 #define CLK_APMIXED_CCIPLL 2 16 #define CLK_APMIXED_MAINPLL 3 17 #define CLK_APMIXED_UNIV2PLL 4 18 #define CLK_APMIXED_MSDCPLL 5 19 #define CLK_APMIXED_MMPLL 6 20 #define CLK_APMIXED_MFGPLL 7 21 #define CLK_APMIXED_TVDPLL 8 22 #define CLK_APMIXED_APLL1 9 23 #define CLK_APMIXED_APLL2 10 24 #define CLK_APMIXED_SSUSB_26M 11 25 #define CLK_APMIXED_APPLL_26M 12 26 #define CLK_APMIXED_MIPIC0_26M 13 27 #define CLK_APMIXED_MDPLLGP_26M 14 28 #define CLK_APMIXED_MMSYS_26M 15 29 #define CLK_APMIXED_UFS_26M 16 30 #define CLK_APMIXED_MIPIC1_26M 17 31 #define CLK_APMIXED_MEMPLL_26M 18 32 #define CLK_APMIXED_CLKSQ_LVPLL_26M 19 33 #define CLK_APMIXED_MIPID0_26M 20 34 #define CLK_APMIXED_MIPID1_26M 21 35 #define CLK_APMIXED_NR_CLK 22 36 37 /* TOPCKGEN */ 38 #define CLK_TOP_MUX_AXI 0 39 #define CLK_TOP_MUX_MM 1 40 #define CLK_TOP_MUX_CAM 2 41 #define CLK_TOP_MUX_MFG 3 42 #define CLK_TOP_MUX_CAMTG 4 43 #define CLK_TOP_MUX_UART 5 44 #define CLK_TOP_MUX_SPI 6 45 #define CLK_TOP_MUX_MSDC50_0_HCLK 7 46 #define CLK_TOP_MUX_MSDC50_0 8 47 #define CLK_TOP_MUX_MSDC30_1 9 48 #define CLK_TOP_MUX_MSDC30_2 10 49 #define CLK_TOP_MUX_AUDIO 11 50 #define CLK_TOP_MUX_AUD_INTBUS 12 51 #define CLK_TOP_MUX_FPWRAP_ULPOSC 13 52 #define CLK_TOP_MUX_SCP 14 53 #define CLK_TOP_MUX_ATB 15 54 #define CLK_TOP_MUX_SSPM 16 55 #define CLK_TOP_MUX_DPI0 17 56 #define CLK_TOP_MUX_SCAM 18 57 #define CLK_TOP_MUX_AUD_1 19 58 #define CLK_TOP_MUX_AUD_2 20 59 #define CLK_TOP_MUX_DISP_PWM 21 60 #define CLK_TOP_MUX_SSUSB_TOP_XHCI 22 61 #define CLK_TOP_MUX_USB_TOP 23 62 #define CLK_TOP_MUX_SPM 24 63 #define CLK_TOP_MUX_I2C 25 64 #define CLK_TOP_MUX_F52M_MFG 26 65 #define CLK_TOP_MUX_SENINF 27 66 #define CLK_TOP_MUX_DXCC 28 67 #define CLK_TOP_MUX_CAMTG2 29 68 #define CLK_TOP_MUX_AUD_ENG1 30 69 #define CLK_TOP_MUX_AUD_ENG2 31 70 #define CLK_TOP_MUX_FAES_UFSFDE 32 71 #define CLK_TOP_MUX_FUFS 33 72 #define CLK_TOP_MUX_IMG 34 73 #define CLK_TOP_MUX_DSP 35 74 #define CLK_TOP_MUX_DSP1 36 75 #define CLK_TOP_MUX_DSP2 37 76 #define CLK_TOP_MUX_IPU_IF 38 77 #define CLK_TOP_MUX_CAMTG3 39 78 #define CLK_TOP_MUX_CAMTG4 40 79 #define CLK_TOP_MUX_PMICSPI 41 80 #define CLK_TOP_SYSPLL_CK 42 81 #define CLK_TOP_SYSPLL_D2 43 82 #define CLK_TOP_SYSPLL_D3 44 83 #define CLK_TOP_SYSPLL_D5 45 84 #define CLK_TOP_SYSPLL_D7 46 85 #define CLK_TOP_SYSPLL_D2_D2 47 86 #define CLK_TOP_SYSPLL_D2_D4 48 87 #define CLK_TOP_SYSPLL_D2_D8 49 88 #define CLK_TOP_SYSPLL_D2_D16 50 89 #define CLK_TOP_SYSPLL_D3_D2 51 90 #define CLK_TOP_SYSPLL_D3_D4 52 91 #define CLK_TOP_SYSPLL_D3_D8 53 92 #define CLK_TOP_SYSPLL_D5_D2 54 93 #define CLK_TOP_SYSPLL_D5_D4 55 94 #define CLK_TOP_SYSPLL_D7_D2 56 95 #define CLK_TOP_SYSPLL_D7_D4 57 96 #define CLK_TOP_UNIVPLL_CK 58 97 #define CLK_TOP_UNIVPLL_D2 59 98 #define CLK_TOP_UNIVPLL_D3 60 99 #define CLK_TOP_UNIVPLL_D5 61 100 #define CLK_TOP_UNIVPLL_D7 62 101 #define CLK_TOP_UNIVPLL_D2_D2 63 102 #define CLK_TOP_UNIVPLL_D2_D4 64 103 #define CLK_TOP_UNIVPLL_D2_D8 65 104 #define CLK_TOP_UNIVPLL_D3_D2 66 105 #define CLK_TOP_UNIVPLL_D3_D4 67 106 #define CLK_TOP_UNIVPLL_D3_D8 68 107 #define CLK_TOP_UNIVPLL_D5_D2 69 108 #define CLK_TOP_UNIVPLL_D5_D4 70 109 #define CLK_TOP_UNIVPLL_D5_D8 71 110 #define CLK_TOP_APLL1_CK 72 111 #define CLK_TOP_APLL1_D2 73 112 #define CLK_TOP_APLL1_D4 74 113 #define CLK_TOP_APLL1_D8 75 114 #define CLK_TOP_APLL2_CK 76 115 #define CLK_TOP_APLL2_D2 77 116 #define CLK_TOP_APLL2_D4 78 117 #define CLK_TOP_APLL2_D8 79 118 #define CLK_TOP_TVDPLL_CK 80 119 #define CLK_TOP_TVDPLL_D2 81 120 #define CLK_TOP_TVDPLL_D4 82 121 #define CLK_TOP_TVDPLL_D8 83 122 #define CLK_TOP_TVDPLL_D16 84 123 #define CLK_TOP_MSDCPLL_CK 85 124 #define CLK_TOP_MSDCPLL_D2 86 125 #define CLK_TOP_MSDCPLL_D4 87 126 #define CLK_TOP_MSDCPLL_D8 88 127 #define CLK_TOP_MSDCPLL_D16 89 128 #define CLK_TOP_AD_OSC_CK 90 129 #define CLK_TOP_OSC_D2 91 130 #define CLK_TOP_OSC_D4 92 131 #define CLK_TOP_OSC_D8 93 132 #define CLK_TOP_OSC_D16 94 133 #define CLK_TOP_F26M_CK_D2 95 134 #define CLK_TOP_MFGPLL_CK 96 135 #define CLK_TOP_UNIVP_192M_CK 97 136 #define CLK_TOP_UNIVP_192M_D2 98 137 #define CLK_TOP_UNIVP_192M_D4 99 138 #define CLK_TOP_UNIVP_192M_D8 100 139 #define CLK_TOP_UNIVP_192M_D16 101 140 #define CLK_TOP_UNIVP_192M_D32 102 141 #define CLK_TOP_MMPLL_CK 103 142 #define CLK_TOP_MMPLL_D4 104 143 #define CLK_TOP_MMPLL_D4_D2 105 144 #define CLK_TOP_MMPLL_D4_D4 106 145 #define CLK_TOP_MMPLL_D5 107 146 #define CLK_TOP_MMPLL_D5_D2 108 147 #define CLK_TOP_MMPLL_D5_D4 109 148 #define CLK_TOP_MMPLL_D6 110 149 #define CLK_TOP_MMPLL_D7 111 150 #define CLK_TOP_CLK26M 112 151 #define CLK_TOP_CLK13M 113 152 #define CLK_TOP_ULPOSC 114 153 #define CLK_TOP_UNIVP_192M 115 154 #define CLK_TOP_MUX_APLL_I2S0 116 155 #define CLK_TOP_MUX_APLL_I2S1 117 156 #define CLK_TOP_MUX_APLL_I2S2 118 157 #define CLK_TOP_MUX_APLL_I2S3 119 158 #define CLK_TOP_MUX_APLL_I2S4 120 159 #define CLK_TOP_MUX_APLL_I2S5 121 160 #define CLK_TOP_APLL12_DIV0 122 161 #define CLK_TOP_APLL12_DIV1 123 162 #define CLK_TOP_APLL12_DIV2 124 163 #define CLK_TOP_APLL12_DIV3 125 164 #define CLK_TOP_APLL12_DIV4 126 165 #define CLK_TOP_APLL12_DIVB 127 166 #define CLK_TOP_UNIVPLL 128 167 #define CLK_TOP_ARMPLL_DIV_PLL1 129 168 #define CLK_TOP_ARMPLL_DIV_PLL2 130 169 #define CLK_TOP_UNIVPLL_D3_D16 131 170 #define CLK_TOP_NR_CLK 132 171 172 /* CAMSYS */ 173 #define CLK_CAM_LARB6 0 174 #define CLK_CAM_DFP_VAD 1 175 #define CLK_CAM_CAM 2 176 #define CLK_CAM_CAMTG 3 177 #define CLK_CAM_SENINF 4 178 #define CLK_CAM_CAMSV0 5 179 #define CLK_CAM_CAMSV1 6 180 #define CLK_CAM_CAMSV2 7 181 #define CLK_CAM_CCU 8 182 #define CLK_CAM_LARB3 9 183 #define CLK_CAM_NR_CLK 10 184 185 /* INFRACFG_AO */ 186 #define CLK_INFRA_PMIC_TMR 0 187 #define CLK_INFRA_PMIC_AP 1 188 #define CLK_INFRA_PMIC_MD 2 189 #define CLK_INFRA_PMIC_CONN 3 190 #define CLK_INFRA_SCPSYS 4 191 #define CLK_INFRA_SEJ 5 192 #define CLK_INFRA_APXGPT 6 193 #define CLK_INFRA_ICUSB 7 194 #define CLK_INFRA_GCE 8 195 #define CLK_INFRA_THERM 9 196 #define CLK_INFRA_I2C0 10 197 #define CLK_INFRA_I2C1 11 198 #define CLK_INFRA_I2C2 12 199 #define CLK_INFRA_I2C3 13 200 #define CLK_INFRA_PWM_HCLK 14 201 #define CLK_INFRA_PWM1 15 202 #define CLK_INFRA_PWM2 16 203 #define CLK_INFRA_PWM3 17 204 #define CLK_INFRA_PWM4 18 205 #define CLK_INFRA_PWM 19 206 #define CLK_INFRA_UART0 20 207 #define CLK_INFRA_UART1 21 208 #define CLK_INFRA_UART2 22 209 #define CLK_INFRA_UART3 23 210 #define CLK_INFRA_GCE_26M 24 211 #define CLK_INFRA_CQ_DMA_FPC 25 212 #define CLK_INFRA_BTIF 26 213 #define CLK_INFRA_SPI0 27 214 #define CLK_INFRA_MSDC0 28 215 #define CLK_INFRA_MSDC1 29 216 #define CLK_INFRA_MSDC2 30 217 #define CLK_INFRA_MSDC0_SCK 31 218 #define CLK_INFRA_DVFSRC 32 219 #define CLK_INFRA_GCPU 33 220 #define CLK_INFRA_TRNG 34 221 #define CLK_INFRA_AUXADC 35 222 #define CLK_INFRA_CPUM 36 223 #define CLK_INFRA_CCIF1_AP 37 224 #define CLK_INFRA_CCIF1_MD 38 225 #define CLK_INFRA_AUXADC_MD 39 226 #define CLK_INFRA_MSDC1_SCK 40 227 #define CLK_INFRA_MSDC2_SCK 41 228 #define CLK_INFRA_AP_DMA 42 229 #define CLK_INFRA_XIU 43 230 #define CLK_INFRA_DEVICE_APC 44 231 #define CLK_INFRA_CCIF_AP 45 232 #define CLK_INFRA_DEBUGSYS 46 233 #define CLK_INFRA_AUDIO 47 234 #define CLK_INFRA_CCIF_MD 48 235 #define CLK_INFRA_DXCC_SEC_CORE 49 236 #define CLK_INFRA_DXCC_AO 50 237 #define CLK_INFRA_DRAMC_F26M 51 238 #define CLK_INFRA_IRTX 52 239 #define CLK_INFRA_DISP_PWM 53 240 #define CLK_INFRA_CLDMA_BCLK 54 241 #define CLK_INFRA_AUDIO_26M_BCLK 55 242 #define CLK_INFRA_SPI1 56 243 #define CLK_INFRA_I2C4 57 244 #define CLK_INFRA_MODEM_TEMP_SHARE 58 245 #define CLK_INFRA_SPI2 59 246 #define CLK_INFRA_SPI3 60 247 #define CLK_INFRA_UNIPRO_SCK 61 248 #define CLK_INFRA_UNIPRO_TICK 62 249 #define CLK_INFRA_UFS_MP_SAP_BCLK 63 250 #define CLK_INFRA_MD32_BCLK 64 251 #define CLK_INFRA_SSPM 65 252 #define CLK_INFRA_UNIPRO_MBIST 66 253 #define CLK_INFRA_SSPM_BUS_HCLK 67 254 #define CLK_INFRA_I2C5 68 255 #define CLK_INFRA_I2C5_ARBITER 69 256 #define CLK_INFRA_I2C5_IMM 70 257 #define CLK_INFRA_I2C1_ARBITER 71 258 #define CLK_INFRA_I2C1_IMM 72 259 #define CLK_INFRA_I2C2_ARBITER 73 260 #define CLK_INFRA_I2C2_IMM 74 261 #define CLK_INFRA_SPI4 75 262 #define CLK_INFRA_SPI5 76 263 #define CLK_INFRA_CQ_DMA 77 264 #define CLK_INFRA_UFS 78 265 #define CLK_INFRA_AES_UFSFDE 79 266 #define CLK_INFRA_UFS_TICK 80 267 #define CLK_INFRA_MSDC0_SELF 81 268 #define CLK_INFRA_MSDC1_SELF 82 269 #define CLK_INFRA_MSDC2_SELF 83 270 #define CLK_INFRA_SSPM_26M_SELF 84 271 #define CLK_INFRA_SSPM_32K_SELF 85 272 #define CLK_INFRA_UFS_AXI 86 273 #define CLK_INFRA_I2C6 87 274 #define CLK_INFRA_AP_MSDC0 88 275 #define CLK_INFRA_MD_MSDC0 89 276 #define CLK_INFRA_USB 90 277 #define CLK_INFRA_DEVMPU_BCLK 91 278 #define CLK_INFRA_CCIF2_AP 92 279 #define CLK_INFRA_CCIF2_MD 93 280 #define CLK_INFRA_CCIF3_AP 94 281 #define CLK_INFRA_CCIF3_MD 95 282 #define CLK_INFRA_SEJ_F13M 96 283 #define CLK_INFRA_AES_BCLK 97 284 #define CLK_INFRA_I2C7 98 285 #define CLK_INFRA_I2C8 99 286 #define CLK_INFRA_FBIST2FPC 100 287 #define CLK_INFRA_NR_CLK 101 288 289 /* PERICFG */ 290 #define CLK_PERI_AXI 0 291 #define CLK_PERI_NR_CLK 1 292 293 /* MFGCFG */ 294 #define CLK_MFG_BG3D 0 295 #define CLK_MFG_NR_CLK 1 296 297 /* IMG */ 298 #define CLK_IMG_OWE 0 299 #define CLK_IMG_WPE_B 1 300 #define CLK_IMG_WPE_A 2 301 #define CLK_IMG_MFB 3 302 #define CLK_IMG_RSC 4 303 #define CLK_IMG_DPE 5 304 #define CLK_IMG_FDVT 6 305 #define CLK_IMG_DIP 7 306 #define CLK_IMG_LARB2 8 307 #define CLK_IMG_LARB5 9 308 #define CLK_IMG_NR_CLK 10 309 310 /* MMSYS_CONFIG */ 311 #define CLK_MM_SMI_COMMON 0 312 #define CLK_MM_SMI_LARB0 1 313 #define CLK_MM_SMI_LARB1 2 314 #define CLK_MM_GALS_COMM0 3 315 #define CLK_MM_GALS_COMM1 4 316 #define CLK_MM_GALS_CCU2MM 5 317 #define CLK_MM_GALS_IPU12MM 6 318 #define CLK_MM_GALS_IMG2MM 7 319 #define CLK_MM_GALS_CAM2MM 8 320 #define CLK_MM_GALS_IPU2MM 9 321 #define CLK_MM_MDP_DL_TXCK 10 322 #define CLK_MM_IPU_DL_TXCK 11 323 #define CLK_MM_MDP_RDMA0 12 324 #define CLK_MM_MDP_RDMA1 13 325 #define CLK_MM_MDP_RSZ0 14 326 #define CLK_MM_MDP_RSZ1 15 327 #define CLK_MM_MDP_TDSHP 16 328 #define CLK_MM_MDP_WROT0 17 329 #define CLK_MM_FAKE_ENG 18 330 #define CLK_MM_DISP_OVL0 19 331 #define CLK_MM_DISP_OVL0_2L 20 332 #define CLK_MM_DISP_OVL1_2L 21 333 #define CLK_MM_DISP_RDMA0 22 334 #define CLK_MM_DISP_RDMA1 23 335 #define CLK_MM_DISP_WDMA0 24 336 #define CLK_MM_DISP_COLOR0 25 337 #define CLK_MM_DISP_CCORR0 26 338 #define CLK_MM_DISP_AAL0 27 339 #define CLK_MM_DISP_GAMMA0 28 340 #define CLK_MM_DISP_DITHER0 29 341 #define CLK_MM_DISP_SPLIT 30 342 #define CLK_MM_DSI0_MM 31 343 #define CLK_MM_DSI0_IF 32 344 #define CLK_MM_DPI_MM 33 345 #define CLK_MM_DPI_IF 34 346 #define CLK_MM_FAKE_ENG2 35 347 #define CLK_MM_MDP_DL_RX 36 348 #define CLK_MM_IPU_DL_RX 37 349 #define CLK_MM_26M 38 350 #define CLK_MM_MMSYS_R2Y 39 351 #define CLK_MM_DISP_RSZ 40 352 #define CLK_MM_MDP_WDMA0 41 353 #define CLK_MM_MDP_AAL 42 354 #define CLK_MM_MDP_CCORR 43 355 #define CLK_MM_DBI_MM 44 356 #define CLK_MM_DBI_IF 45 357 #define CLK_MM_NR_CLK 46 358 359 /* VDEC_GCON */ 360 #define CLK_VDEC_VDEC 0 361 #define CLK_VDEC_LARB1 1 362 #define CLK_VDEC_NR_CLK 2 363 364 /* VENC_GCON */ 365 #define CLK_VENC_LARB 0 366 #define CLK_VENC_VENC 1 367 #define CLK_VENC_JPGENC 2 368 #define CLK_VENC_NR_CLK 3 369 370 /* AUDIO */ 371 #define CLK_AUDIO_TML 0 372 #define CLK_AUDIO_DAC_PREDIS 1 373 #define CLK_AUDIO_DAC 2 374 #define CLK_AUDIO_ADC 3 375 #define CLK_AUDIO_APLL_TUNER 4 376 #define CLK_AUDIO_APLL2_TUNER 5 377 #define CLK_AUDIO_24M 6 378 #define CLK_AUDIO_22M 7 379 #define CLK_AUDIO_AFE 8 380 #define CLK_AUDIO_I2S4 9 381 #define CLK_AUDIO_I2S3 10 382 #define CLK_AUDIO_I2S2 11 383 #define CLK_AUDIO_I2S1 12 384 #define CLK_AUDIO_PDN_ADDA6_ADC 13 385 #define CLK_AUDIO_TDM 14 386 #define CLK_AUDIO_NR_CLK 15 387 388 /* IPU_CONN */ 389 #define CLK_IPU_CONN_IPU 0 390 #define CLK_IPU_CONN_AHB 1 391 #define CLK_IPU_CONN_AXI 2 392 #define CLK_IPU_CONN_ISP 3 393 #define CLK_IPU_CONN_CAM_ADL 4 394 #define CLK_IPU_CONN_IMG_ADL 5 395 #define CLK_IPU_CONN_DAP_RX 6 396 #define CLK_IPU_CONN_APB2AXI 7 397 #define CLK_IPU_CONN_APB2AHB 8 398 #define CLK_IPU_CONN_IPU_CAB1TO2 9 399 #define CLK_IPU_CONN_IPU1_CAB1TO2 10 400 #define CLK_IPU_CONN_IPU2_CAB1TO2 11 401 #define CLK_IPU_CONN_CAB3TO3 12 402 #define CLK_IPU_CONN_CAB2TO1 13 403 #define CLK_IPU_CONN_CAB3TO1_SLICE 14 404 #define CLK_IPU_CONN_NR_CLK 15 405 406 /* IPU_ADL */ 407 #define CLK_IPU_ADL_CABGEN 0 408 #define CLK_IPU_ADL_NR_CLK 1 409 410 /* IPU_CORE0 */ 411 #define CLK_IPU_CORE0_JTAG 0 412 #define CLK_IPU_CORE0_AXI 1 413 #define CLK_IPU_CORE0_IPU 2 414 #define CLK_IPU_CORE0_NR_CLK 3 415 416 /* IPU_CORE1 */ 417 #define CLK_IPU_CORE1_JTAG 0 418 #define CLK_IPU_CORE1_AXI 1 419 #define CLK_IPU_CORE1_IPU 2 420 #define CLK_IPU_CORE1_NR_CLK 3 421 422 /* MCUCFG */ 423 #define CLK_MCU_MP0_SEL 0 424 #define CLK_MCU_MP2_SEL 1 425 #define CLK_MCU_BUS_SEL 2 426 #define CLK_MCU_NR_CLK 3 427 428 #endif /* _DT_BINDINGS_CLK_MT8183_H */ 429
Indexes created Sat Sep 27 22:09:54 GMT 2025