1 /* $NetBSD: mt8516-clk.h,v 1.1.1.1 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2019 MediaTek Inc. 6 * Copyright (c) 2019 BayLibre, SAS. 7 * Author: James Liao <jamesjj.liao (at) mediatek.com> 8 */ 9 10 #ifndef _DT_BINDINGS_CLK_MT8516_H 11 #define _DT_BINDINGS_CLK_MT8516_H 12 13 /* APMIXEDSYS */ 14 15 #define CLK_APMIXED_ARMPLL 0 16 #define CLK_APMIXED_MAINPLL 1 17 #define CLK_APMIXED_UNIVPLL 2 18 #define CLK_APMIXED_MMPLL 3 19 #define CLK_APMIXED_APLL1 4 20 #define CLK_APMIXED_APLL2 5 21 #define CLK_APMIXED_NR_CLK 6 22 23 /* INFRACFG */ 24 25 #define CLK_IFR_MUX1_SEL 0 26 #define CLK_IFR_ETH_25M_SEL 1 27 #define CLK_IFR_I2C0_SEL 2 28 #define CLK_IFR_I2C1_SEL 3 29 #define CLK_IFR_I2C2_SEL 4 30 #define CLK_IFR_NR_CLK 5 31 32 /* TOPCKGEN */ 33 34 #define CLK_TOP_CLK_NULL 0 35 #define CLK_TOP_I2S_INFRA_BCK 1 36 #define CLK_TOP_MEMPLL 2 37 #define CLK_TOP_DMPLL 3 38 #define CLK_TOP_MAINPLL_D2 4 39 #define CLK_TOP_MAINPLL_D4 5 40 #define CLK_TOP_MAINPLL_D8 6 41 #define CLK_TOP_MAINPLL_D16 7 42 #define CLK_TOP_MAINPLL_D11 8 43 #define CLK_TOP_MAINPLL_D22 9 44 #define CLK_TOP_MAINPLL_D3 10 45 #define CLK_TOP_MAINPLL_D6 11 46 #define CLK_TOP_MAINPLL_D12 12 47 #define CLK_TOP_MAINPLL_D5 13 48 #define CLK_TOP_MAINPLL_D10 14 49 #define CLK_TOP_MAINPLL_D20 15 50 #define CLK_TOP_MAINPLL_D40 16 51 #define CLK_TOP_MAINPLL_D7 17 52 #define CLK_TOP_MAINPLL_D14 18 53 #define CLK_TOP_UNIVPLL_D2 19 54 #define CLK_TOP_UNIVPLL_D4 20 55 #define CLK_TOP_UNIVPLL_D8 21 56 #define CLK_TOP_UNIVPLL_D16 22 57 #define CLK_TOP_UNIVPLL_D3 23 58 #define CLK_TOP_UNIVPLL_D6 24 59 #define CLK_TOP_UNIVPLL_D12 25 60 #define CLK_TOP_UNIVPLL_D24 26 61 #define CLK_TOP_UNIVPLL_D5 27 62 #define CLK_TOP_UNIVPLL_D20 28 63 #define CLK_TOP_MMPLL380M 29 64 #define CLK_TOP_MMPLL_D2 30 65 #define CLK_TOP_MMPLL_200M 31 66 #define CLK_TOP_USB_PHY48M 32 67 #define CLK_TOP_APLL1 33 68 #define CLK_TOP_APLL1_D2 34 69 #define CLK_TOP_APLL1_D4 35 70 #define CLK_TOP_APLL1_D8 36 71 #define CLK_TOP_APLL2 37 72 #define CLK_TOP_APLL2_D2 38 73 #define CLK_TOP_APLL2_D4 39 74 #define CLK_TOP_APLL2_D8 40 75 #define CLK_TOP_CLK26M 41 76 #define CLK_TOP_CLK26M_D2 42 77 #define CLK_TOP_AHB_INFRA_D2 43 78 #define CLK_TOP_NFI1X 44 79 #define CLK_TOP_ETH_D2 45 80 #define CLK_TOP_THEM 46 81 #define CLK_TOP_APDMA 47 82 #define CLK_TOP_I2C0 48 83 #define CLK_TOP_I2C1 49 84 #define CLK_TOP_AUXADC1 50 85 #define CLK_TOP_NFI 51 86 #define CLK_TOP_NFIECC 52 87 #define CLK_TOP_DEBUGSYS 53 88 #define CLK_TOP_PWM 54 89 #define CLK_TOP_UART0 55 90 #define CLK_TOP_UART1 56 91 #define CLK_TOP_BTIF 57 92 #define CLK_TOP_USB 58 93 #define CLK_TOP_FLASHIF_26M 59 94 #define CLK_TOP_AUXADC2 60 95 #define CLK_TOP_I2C2 61 96 #define CLK_TOP_MSDC0 62 97 #define CLK_TOP_MSDC1 63 98 #define CLK_TOP_NFI2X 64 99 #define CLK_TOP_PMICWRAP_AP 65 100 #define CLK_TOP_SEJ 66 101 #define CLK_TOP_MEMSLP_DLYER 67 102 #define CLK_TOP_SPI 68 103 #define CLK_TOP_APXGPT 69 104 #define CLK_TOP_AUDIO 70 105 #define CLK_TOP_PMICWRAP_MD 71 106 #define CLK_TOP_PMICWRAP_CONN 72 107 #define CLK_TOP_PMICWRAP_26M 73 108 #define CLK_TOP_AUX_ADC 74 109 #define CLK_TOP_AUX_TP 75 110 #define CLK_TOP_MSDC2 76 111 #define CLK_TOP_RBIST 77 112 #define CLK_TOP_NFI_BUS 78 113 #define CLK_TOP_GCE 79 114 #define CLK_TOP_TRNG 80 115 #define CLK_TOP_SEJ_13M 81 116 #define CLK_TOP_AES 82 117 #define CLK_TOP_PWM_B 83 118 #define CLK_TOP_PWM1_FB 84 119 #define CLK_TOP_PWM2_FB 85 120 #define CLK_TOP_PWM3_FB 86 121 #define CLK_TOP_PWM4_FB 87 122 #define CLK_TOP_PWM5_FB 88 123 #define CLK_TOP_USB_1P 89 124 #define CLK_TOP_FLASHIF_FREERUN 90 125 #define CLK_TOP_66M_ETH 91 126 #define CLK_TOP_133M_ETH 92 127 #define CLK_TOP_FETH_25M 93 128 #define CLK_TOP_FETH_50M 94 129 #define CLK_TOP_FLASHIF_AXI 95 130 #define CLK_TOP_USBIF 96 131 #define CLK_TOP_UART2 97 132 #define CLK_TOP_BSI 98 133 #define CLK_TOP_RG_SPINOR 99 134 #define CLK_TOP_RG_MSDC2 100 135 #define CLK_TOP_RG_ETH 101 136 #define CLK_TOP_RG_AUD1 102 137 #define CLK_TOP_RG_AUD2 103 138 #define CLK_TOP_RG_AUD_ENGEN1 104 139 #define CLK_TOP_RG_AUD_ENGEN2 105 140 #define CLK_TOP_RG_I2C 106 141 #define CLK_TOP_RG_PWM_INFRA 107 142 #define CLK_TOP_RG_AUD_SPDIF_IN 108 143 #define CLK_TOP_RG_UART2 109 144 #define CLK_TOP_RG_BSI 110 145 #define CLK_TOP_RG_DBG_ATCLK 111 146 #define CLK_TOP_RG_NFIECC 112 147 #define CLK_TOP_RG_APLL1_D2_EN 113 148 #define CLK_TOP_RG_APLL1_D4_EN 114 149 #define CLK_TOP_RG_APLL1_D8_EN 115 150 #define CLK_TOP_RG_APLL2_D2_EN 116 151 #define CLK_TOP_RG_APLL2_D4_EN 117 152 #define CLK_TOP_RG_APLL2_D8_EN 118 153 #define CLK_TOP_APLL12_DIV0 119 154 #define CLK_TOP_APLL12_DIV1 120 155 #define CLK_TOP_APLL12_DIV2 121 156 #define CLK_TOP_APLL12_DIV3 122 157 #define CLK_TOP_APLL12_DIV4 123 158 #define CLK_TOP_APLL12_DIV4B 124 159 #define CLK_TOP_APLL12_DIV5 125 160 #define CLK_TOP_APLL12_DIV5B 126 161 #define CLK_TOP_APLL12_DIV6 127 162 #define CLK_TOP_UART0_SEL 128 163 #define CLK_TOP_EMI_DDRPHY_SEL 129 164 #define CLK_TOP_AHB_INFRA_SEL 130 165 #define CLK_TOP_MSDC0_SEL 131 166 #define CLK_TOP_UART1_SEL 132 167 #define CLK_TOP_MSDC1_SEL 133 168 #define CLK_TOP_PMICSPI_SEL 134 169 #define CLK_TOP_QAXI_AUD26M_SEL 135 170 #define CLK_TOP_AUD_INTBUS_SEL 136 171 #define CLK_TOP_NFI2X_PAD_SEL 137 172 #define CLK_TOP_NFI1X_PAD_SEL 138 173 #define CLK_TOP_DDRPHYCFG_SEL 139 174 #define CLK_TOP_USB_78M_SEL 140 175 #define CLK_TOP_SPINOR_SEL 141 176 #define CLK_TOP_MSDC2_SEL 142 177 #define CLK_TOP_ETH_SEL 143 178 #define CLK_TOP_AUD1_SEL 144 179 #define CLK_TOP_AUD2_SEL 145 180 #define CLK_TOP_AUD_ENGEN1_SEL 146 181 #define CLK_TOP_AUD_ENGEN2_SEL 147 182 #define CLK_TOP_I2C_SEL 148 183 #define CLK_TOP_AUD_I2S0_M_SEL 149 184 #define CLK_TOP_AUD_I2S1_M_SEL 150 185 #define CLK_TOP_AUD_I2S2_M_SEL 151 186 #define CLK_TOP_AUD_I2S3_M_SEL 152 187 #define CLK_TOP_AUD_I2S4_M_SEL 153 188 #define CLK_TOP_AUD_I2S5_M_SEL 154 189 #define CLK_TOP_AUD_SPDIF_B_SEL 155 190 #define CLK_TOP_PWM_SEL 156 191 #define CLK_TOP_SPI_SEL 157 192 #define CLK_TOP_AUD_SPDIFIN_SEL 158 193 #define CLK_TOP_UART2_SEL 159 194 #define CLK_TOP_BSI_SEL 160 195 #define CLK_TOP_DBG_ATCLK_SEL 161 196 #define CLK_TOP_CSW_NFIECC_SEL 162 197 #define CLK_TOP_NFIECC_SEL 163 198 #define CLK_TOP_APLL12_CK_DIV0 164 199 #define CLK_TOP_APLL12_CK_DIV1 165 200 #define CLK_TOP_APLL12_CK_DIV2 166 201 #define CLK_TOP_APLL12_CK_DIV3 167 202 #define CLK_TOP_APLL12_CK_DIV4 168 203 #define CLK_TOP_APLL12_CK_DIV4B 169 204 #define CLK_TOP_APLL12_CK_DIV5 170 205 #define CLK_TOP_APLL12_CK_DIV5B 171 206 #define CLK_TOP_APLL12_CK_DIV6 172 207 #define CLK_TOP_USB_78M 173 208 #define CLK_TOP_MSDC0_INFRA 174 209 #define CLK_TOP_MSDC1_INFRA 175 210 #define CLK_TOP_MSDC2_INFRA 176 211 #define CLK_TOP_NR_CLK 177 212 213 /* AUDSYS */ 214 215 #define CLK_AUD_AFE 0 216 #define CLK_AUD_I2S 1 217 #define CLK_AUD_22M 2 218 #define CLK_AUD_24M 3 219 #define CLK_AUD_INTDIR 4 220 #define CLK_AUD_APLL2_TUNER 5 221 #define CLK_AUD_APLL_TUNER 6 222 #define CLK_AUD_HDMI 7 223 #define CLK_AUD_SPDF 8 224 #define CLK_AUD_ADC 9 225 #define CLK_AUD_DAC 10 226 #define CLK_AUD_DAC_PREDIS 11 227 #define CLK_AUD_TML 12 228 #define CLK_AUD_NR_CLK 13 229 230 #endif /* _DT_BINDINGS_CLK_MT8516_H */ 231
Indexes created Sun Sep 28 16:09:52 GMT 2025