1/* $NetBSD: nuvoton,ma35d1-clk.h,v 1.1.1.1 2026/01/18 05:21:33 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 4/* 5 * Copyright (C) 2023 Nuvoton Technologies. 6 */ 7 8#ifndef __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H 9#define __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H 10 11/* external and internal oscillator clocks */ 12#define HXT 0 13#define HXT_GATE 1 14#define LXT 2 15#define LXT_GATE 3 16#define HIRC 4 17#define HIRC_GATE 5 18#define LIRC 6 19#define LIRC_GATE 7 20/* PLLs */ 21#define CAPLL 8 22#define SYSPLL 9 23#define DDRPLL 10 24#define APLL 11 25#define EPLL 12 26#define VPLL 13 27/* EPLL divider */ 28#define EPLL_DIV2 14 29#define EPLL_DIV4 15 30#define EPLL_DIV8 16 31/* CPU clock, system clock, AXI, HCLK and PCLK */ 32#define CA35CLK_MUX 17 33#define AXICLK_DIV2 18 34#define AXICLK_DIV4 19 35#define AXICLK_MUX 20 36#define SYSCLK0_MUX 21 37#define SYSCLK1_MUX 22 38#define SYSCLK1_DIV2 23 39#define HCLK0 24 40#define HCLK1 25 41#define HCLK2 26 42#define PCLK0 27 43#define PCLK1 28 44#define PCLK2 29 45#define HCLK3 30 46#define PCLK3 31 47#define PCLK4 32 48/* AXI and AHB peripheral clocks */ 49#define USBPHY0 33 50#define USBPHY1 34 51#define DDR0_GATE 35 52#define DDR6_GATE 36 53#define CAN0_MUX 37 54#define CAN0_DIV 38 55#define CAN0_GATE 39 56#define CAN1_MUX 40 57#define CAN1_DIV 41 58#define CAN1_GATE 42 59#define CAN2_MUX 43 60#define CAN2_DIV 44 61#define CAN2_GATE 45 62#define CAN3_MUX 46 63#define CAN3_DIV 47 64#define CAN3_GATE 48 65#define SDH0_MUX 49 66#define SDH0_GATE 50 67#define SDH1_MUX 51 68#define SDH1_GATE 52 69#define NAND_GATE 53 70#define USBD_GATE 54 71#define USBH_GATE 55 72#define HUSBH0_GATE 56 73#define HUSBH1_GATE 57 74#define GFX_MUX 58 75#define GFX_GATE 59 76#define VC8K_GATE 60 77#define DCU_MUX 61 78#define DCU_GATE 62 79#define DCUP_DIV 63 80#define EMAC0_GATE 64 81#define EMAC1_GATE 65 82#define CCAP0_MUX 66 83#define CCAP0_DIV 67 84#define CCAP0_GATE 68 85#define CCAP1_MUX 69 86#define CCAP1_DIV 70 87#define CCAP1_GATE 71 88#define PDMA0_GATE 72 89#define PDMA1_GATE 73 90#define PDMA2_GATE 74 91#define PDMA3_GATE 75 92#define WH0_GATE 76 93#define WH1_GATE 77 94#define HWS_GATE 78 95#define EBI_GATE 79 96#define SRAM0_GATE 80 97#define SRAM1_GATE 81 98#define ROM_GATE 82 99#define TRA_GATE 83 100#define DBG_MUX 84 101#define DBG_GATE 85 102#define CKO_MUX 86 103#define CKO_DIV 87 104#define CKO_GATE 88 105#define GTMR_GATE 89 106#define GPA_GATE 90 107#define GPB_GATE 91 108#define GPC_GATE 92 109#define GPD_GATE 93 110#define GPE_GATE 94 111#define GPF_GATE 95 112#define GPG_GATE 96 113#define GPH_GATE 97 114#define GPI_GATE 98 115#define GPJ_GATE 99 116#define GPK_GATE 100 117#define GPL_GATE 101 118#define GPM_GATE 102 119#define GPN_GATE 103 120/* APB peripheral clocks */ 121#define TMR0_MUX 104 122#define TMR0_GATE 105 123#define TMR1_MUX 106 124#define TMR1_GATE 107 125#define TMR2_MUX 108 126#define TMR2_GATE 109 127#define TMR3_MUX 110 128#define TMR3_GATE 111 129#define TMR4_MUX 112 130#define TMR4_GATE 113 131#define TMR5_MUX 114 132#define TMR5_GATE 115 133#define TMR6_MUX 116 134#define TMR6_GATE 117 135#define TMR7_MUX 118 136#define TMR7_GATE 119 137#define TMR8_MUX 120 138#define TMR8_GATE 121 139#define TMR9_MUX 122 140#define TMR9_GATE 123 141#define TMR10_MUX 124 142#define TMR10_GATE 125 143#define TMR11_MUX 126 144#define TMR11_GATE 127 145#define UART0_MUX 128 146#define UART0_DIV 129 147#define UART0_GATE 130 148#define UART1_MUX 131 149#define UART1_DIV 132 150#define UART1_GATE 133 151#define UART2_MUX 134 152#define UART2_DIV 135 153#define UART2_GATE 136 154#define UART3_MUX 137 155#define UART3_DIV 138 156#define UART3_GATE 139 157#define UART4_MUX 140 158#define UART4_DIV 141 159#define UART4_GATE 142 160#define UART5_MUX 143 161#define UART5_DIV 144 162#define UART5_GATE 145 163#define UART6_MUX 146 164#define UART6_DIV 147 165#define UART6_GATE 148 166#define UART7_MUX 149 167#define UART7_DIV 150 168#define UART7_GATE 151 169#define UART8_MUX 152 170#define UART8_DIV 153 171#define UART8_GATE 154 172#define UART9_MUX 155 173#define UART9_DIV 156 174#define UART9_GATE 157 175#define UART10_MUX 158 176#define UART10_DIV 159 177#define UART10_GATE 160 178#define UART11_MUX 161 179#define UART11_DIV 162 180#define UART11_GATE 163 181#define UART12_MUX 164 182#define UART12_DIV 165 183#define UART12_GATE 166 184#define UART13_MUX 167 185#define UART13_DIV 168 186#define UART13_GATE 169 187#define UART14_MUX 170 188#define UART14_DIV 171 189#define UART14_GATE 172 190#define UART15_MUX 173 191#define UART15_DIV 174 192#define UART15_GATE 175 193#define UART16_MUX 176 194#define UART16_DIV 177 195#define UART16_GATE 178 196#define RTC_GATE 179 197#define DDR_GATE 180 198#define KPI_MUX 181 199#define KPI_DIV 182 200#define KPI_GATE 183 201#define I2C0_GATE 184 202#define I2C1_GATE 185 203#define I2C2_GATE 186 204#define I2C3_GATE 187 205#define I2C4_GATE 188 206#define I2C5_GATE 189 207#define QSPI0_MUX 190 208#define QSPI0_GATE 191 209#define QSPI1_MUX 192 210#define QSPI1_GATE 193 211#define SMC0_MUX 194 212#define SMC0_DIV 195 213#define SMC0_GATE 196 214#define SMC1_MUX 197 215#define SMC1_DIV 198 216#define SMC1_GATE 199 217#define WDT0_MUX 200 218#define WDT0_GATE 201 219#define WDT1_MUX 202 220#define WDT1_GATE 203 221#define WDT2_MUX 204 222#define WDT2_GATE 205 223#define WWDT0_MUX 206 224#define WWDT1_MUX 207 225#define WWDT2_MUX 208 226#define EPWM0_GATE 209 227#define EPWM1_GATE 210 228#define EPWM2_GATE 211 229#define I2S0_MUX 212 230#define I2S0_GATE 213 231#define I2S1_MUX 214 232#define I2S1_GATE 215 233#define SSMCC_GATE 216 234#define SSPCC_GATE 217 235#define SPI0_MUX 218 236#define SPI0_GATE 219 237#define SPI1_MUX 220 238#define SPI1_GATE 221 239#define SPI2_MUX 222 240#define SPI2_GATE 223 241#define SPI3_MUX 224 242#define SPI3_GATE 225 243#define ECAP0_GATE 226 244#define ECAP1_GATE 227 245#define ECAP2_GATE 228 246#define QEI0_GATE 229 247#define QEI1_GATE 230 248#define QEI2_GATE 231 249#define ADC_DIV 232 250#define ADC_GATE 233 251#define EADC_DIV 234 252#define EADC_GATE 235 253#define CLK_MAX_IDX 236 254 255#endif /* __DT_BINDINGS_CLOCK_NUVOTON_MA35D1_CLK_H */ 256