1/* $NetBSD: qcom,gcc-ipq5018.h,v 1.1.1.1 2026/01/18 05:21:34 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2023, The Linux Foundation. All rights reserved. 6 */ 7 8#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H 9#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H 10 11#define GPLL0_MAIN 0 12#define GPLL0 1 13#define GPLL2_MAIN 2 14#define GPLL2 3 15#define GPLL4_MAIN 4 16#define GPLL4 5 17#define UBI32_PLL_MAIN 6 18#define UBI32_PLL 7 19#define ADSS_PWM_CLK_SRC 8 20#define BLSP1_QUP1_I2C_APPS_CLK_SRC 9 21#define BLSP1_QUP1_SPI_APPS_CLK_SRC 10 22#define BLSP1_QUP2_I2C_APPS_CLK_SRC 11 23#define BLSP1_QUP2_SPI_APPS_CLK_SRC 12 24#define BLSP1_QUP3_I2C_APPS_CLK_SRC 13 25#define BLSP1_QUP3_SPI_APPS_CLK_SRC 14 26#define BLSP1_UART1_APPS_CLK_SRC 15 27#define BLSP1_UART2_APPS_CLK_SRC 16 28#define CRYPTO_CLK_SRC 17 29#define GCC_ADSS_PWM_CLK 18 30#define GCC_BLSP1_AHB_CLK 19 31#define GCC_BLSP1_QUP1_I2C_APPS_CLK 20 32#define GCC_BLSP1_QUP1_SPI_APPS_CLK 21 33#define GCC_BLSP1_QUP2_I2C_APPS_CLK 22 34#define GCC_BLSP1_QUP2_SPI_APPS_CLK 23 35#define GCC_BLSP1_QUP3_I2C_APPS_CLK 24 36#define GCC_BLSP1_QUP3_SPI_APPS_CLK 25 37#define GCC_BLSP1_UART1_APPS_CLK 26 38#define GCC_BLSP1_UART2_APPS_CLK 27 39#define GCC_BTSS_LPO_CLK 28 40#define GCC_CMN_BLK_AHB_CLK 29 41#define GCC_CMN_BLK_SYS_CLK 30 42#define GCC_CRYPTO_AHB_CLK 31 43#define GCC_CRYPTO_AXI_CLK 32 44#define GCC_CRYPTO_CLK 33 45#define GCC_CRYPTO_PPE_CLK 34 46#define GCC_DCC_CLK 35 47#define GCC_GEPHY_RX_CLK 36 48#define GCC_GEPHY_TX_CLK 37 49#define GCC_GMAC0_CFG_CLK 38 50#define GCC_GMAC0_PTP_CLK 39 51#define GCC_GMAC0_RX_CLK 40 52#define GCC_GMAC0_SYS_CLK 41 53#define GCC_GMAC0_TX_CLK 42 54#define GCC_GMAC1_CFG_CLK 43 55#define GCC_GMAC1_PTP_CLK 44 56#define GCC_GMAC1_RX_CLK 45 57#define GCC_GMAC1_SYS_CLK 46 58#define GCC_GMAC1_TX_CLK 47 59#define GCC_GP1_CLK 48 60#define GCC_GP2_CLK 49 61#define GCC_GP3_CLK 50 62#define GCC_LPASS_CORE_AXIM_CLK 51 63#define GCC_LPASS_SWAY_CLK 52 64#define GCC_MDIO0_AHB_CLK 53 65#define GCC_MDIO1_AHB_CLK 54 66#define GCC_PCIE0_AHB_CLK 55 67#define GCC_PCIE0_AUX_CLK 56 68#define GCC_PCIE0_AXI_M_CLK 57 69#define GCC_PCIE0_AXI_S_BRIDGE_CLK 58 70#define GCC_PCIE0_AXI_S_CLK 59 71#define GCC_PCIE0_PIPE_CLK 60 72#define GCC_PCIE1_AHB_CLK 61 73#define GCC_PCIE1_AUX_CLK 62 74#define GCC_PCIE1_AXI_M_CLK 63 75#define GCC_PCIE1_AXI_S_BRIDGE_CLK 64 76#define GCC_PCIE1_AXI_S_CLK 65 77#define GCC_PCIE1_PIPE_CLK 66 78#define GCC_PRNG_AHB_CLK 67 79#define GCC_Q6_AXIM_CLK 68 80#define GCC_Q6_AXIM2_CLK 69 81#define GCC_Q6_AXIS_CLK 70 82#define GCC_Q6_AHB_CLK 71 83#define GCC_Q6_AHB_S_CLK 72 84#define GCC_Q6_TSCTR_1TO2_CLK 73 85#define GCC_Q6SS_ATBM_CLK 74 86#define GCC_Q6SS_PCLKDBG_CLK 75 87#define GCC_Q6SS_TRIG_CLK 76 88#define GCC_QDSS_AT_CLK 77 89#define GCC_QDSS_CFG_AHB_CLK 78 90#define GCC_QDSS_DAP_AHB_CLK 79 91#define GCC_QDSS_DAP_CLK 80 92#define GCC_QDSS_ETR_USB_CLK 81 93#define GCC_QDSS_EUD_AT_CLK 82 94#define GCC_QDSS_STM_CLK 83 95#define GCC_QDSS_TRACECLKIN_CLK 84 96#define GCC_QDSS_TSCTR_DIV8_CLK 85 97#define GCC_QPIC_AHB_CLK 86 98#define GCC_QPIC_CLK 87 99#define GCC_QPIC_IO_MACRO_CLK 88 100#define GCC_SDCC1_AHB_CLK 89 101#define GCC_SDCC1_APPS_CLK 90 102#define GCC_SLEEP_CLK_SRC 91 103#define GCC_SNOC_GMAC0_AHB_CLK 92 104#define GCC_SNOC_GMAC0_AXI_CLK 93 105#define GCC_SNOC_GMAC1_AHB_CLK 94 106#define GCC_SNOC_GMAC1_AXI_CLK 95 107#define GCC_SNOC_LPASS_AXIM_CLK 96 108#define GCC_SNOC_LPASS_SWAY_CLK 97 109#define GCC_SNOC_UBI0_AXI_CLK 98 110#define GCC_SYS_NOC_PCIE0_AXI_CLK 99 111#define GCC_SYS_NOC_PCIE1_AXI_CLK 100 112#define GCC_SYS_NOC_QDSS_STM_AXI_CLK 101 113#define GCC_SYS_NOC_USB0_AXI_CLK 102 114#define GCC_SYS_NOC_WCSS_AHB_CLK 103 115#define GCC_UBI0_AXI_CLK 104 116#define GCC_UBI0_CFG_CLK 105 117#define GCC_UBI0_CORE_CLK 106 118#define GCC_UBI0_DBG_CLK 107 119#define GCC_UBI0_NC_AXI_CLK 108 120#define GCC_UBI0_UTCM_CLK 109 121#define GCC_UNIPHY_AHB_CLK 110 122#define GCC_UNIPHY_RX_CLK 111 123#define GCC_UNIPHY_SYS_CLK 112 124#define GCC_UNIPHY_TX_CLK 113 125#define GCC_USB0_AUX_CLK 114 126#define GCC_USB0_EUD_AT_CLK 115 127#define GCC_USB0_LFPS_CLK 116 128#define GCC_USB0_MASTER_CLK 117 129#define GCC_USB0_MOCK_UTMI_CLK 118 130#define GCC_USB0_PHY_CFG_AHB_CLK 119 131#define GCC_USB0_SLEEP_CLK 120 132#define GCC_WCSS_ACMT_CLK 121 133#define GCC_WCSS_AHB_S_CLK 122 134#define GCC_WCSS_AXI_M_CLK 123 135#define GCC_WCSS_AXI_S_CLK 124 136#define GCC_WCSS_DBG_IFC_APB_BDG_CLK 125 137#define GCC_WCSS_DBG_IFC_APB_CLK 126 138#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK 127 139#define GCC_WCSS_DBG_IFC_ATB_CLK 128 140#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK 129 141#define GCC_WCSS_DBG_IFC_DAPBUS_CLK 130 142#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK 131 143#define GCC_WCSS_DBG_IFC_NTS_CLK 132 144#define GCC_WCSS_ECAHB_CLK 133 145#define GCC_XO_CLK 134 146#define GCC_XO_CLK_SRC 135 147#define GMAC0_RX_CLK_SRC 136 148#define GMAC0_TX_CLK_SRC 137 149#define GMAC1_RX_CLK_SRC 138 150#define GMAC1_TX_CLK_SRC 139 151#define GMAC_CLK_SRC 140 152#define GP1_CLK_SRC 141 153#define GP2_CLK_SRC 142 154#define GP3_CLK_SRC 143 155#define LPASS_AXIM_CLK_SRC 144 156#define LPASS_SWAY_CLK_SRC 145 157#define PCIE0_AUX_CLK_SRC 146 158#define PCIE0_AXI_CLK_SRC 147 159#define PCIE1_AUX_CLK_SRC 148 160#define PCIE1_AXI_CLK_SRC 149 161#define PCNOC_BFDCD_CLK_SRC 150 162#define Q6_AXI_CLK_SRC 151 163#define QDSS_AT_CLK_SRC 152 164#define QDSS_STM_CLK_SRC 153 165#define QDSS_TSCTR_CLK_SRC 154 166#define QDSS_TRACECLKIN_CLK_SRC 155 167#define QPIC_IO_MACRO_CLK_SRC 156 168#define SDCC1_APPS_CLK_SRC 157 169#define SYSTEM_NOC_BFDCD_CLK_SRC 158 170#define UBI0_AXI_CLK_SRC 159 171#define UBI0_CORE_CLK_SRC 160 172#define USB0_AUX_CLK_SRC 161 173#define USB0_LFPS_CLK_SRC 162 174#define USB0_MASTER_CLK_SRC 163 175#define USB0_MOCK_UTMI_CLK_SRC 164 176#define WCSS_AHB_CLK_SRC 165 177#define PCIE0_PIPE_CLK_SRC 166 178#define PCIE1_PIPE_CLK_SRC 167 179#define USB0_PIPE_CLK_SRC 168 180#define GCC_USB0_PIPE_CLK 169 181#define GMAC0_RX_DIV_CLK_SRC 170 182#define GMAC0_TX_DIV_CLK_SRC 171 183#define GMAC1_RX_DIV_CLK_SRC 172 184#define GMAC1_TX_DIV_CLK_SRC 173 185#endif 186