1/* $NetBSD: qcom,sm4450-camcc.h,v 1.1.1.1 2026/01/18 05:21:36 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H 9#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H 10 11/* CAM_CC clocks */ 12#define CAM_CC_BPS_AHB_CLK 0 13#define CAM_CC_BPS_AREG_CLK 1 14#define CAM_CC_BPS_CLK 2 15#define CAM_CC_BPS_CLK_SRC 3 16#define CAM_CC_CAMNOC_ATB_CLK 4 17#define CAM_CC_CAMNOC_AXI_CLK 5 18#define CAM_CC_CAMNOC_AXI_CLK_SRC 6 19#define CAM_CC_CAMNOC_AXI_HF_CLK 7 20#define CAM_CC_CAMNOC_AXI_SF_CLK 8 21#define CAM_CC_CCI_0_CLK 9 22#define CAM_CC_CCI_0_CLK_SRC 10 23#define CAM_CC_CCI_1_CLK 11 24#define CAM_CC_CCI_1_CLK_SRC 12 25#define CAM_CC_CORE_AHB_CLK 13 26#define CAM_CC_CPAS_AHB_CLK 14 27#define CAM_CC_CPHY_RX_CLK_SRC 15 28#define CAM_CC_CRE_AHB_CLK 16 29#define CAM_CC_CRE_CLK 17 30#define CAM_CC_CRE_CLK_SRC 18 31#define CAM_CC_CSI0PHYTIMER_CLK 19 32#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20 33#define CAM_CC_CSI1PHYTIMER_CLK 21 34#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22 35#define CAM_CC_CSI2PHYTIMER_CLK 23 36#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24 37#define CAM_CC_CSIPHY0_CLK 25 38#define CAM_CC_CSIPHY1_CLK 26 39#define CAM_CC_CSIPHY2_CLK 27 40#define CAM_CC_FAST_AHB_CLK_SRC 28 41#define CAM_CC_ICP_ATB_CLK 29 42#define CAM_CC_ICP_CLK 30 43#define CAM_CC_ICP_CLK_SRC 31 44#define CAM_CC_ICP_CTI_CLK 32 45#define CAM_CC_ICP_TS_CLK 33 46#define CAM_CC_MCLK0_CLK 34 47#define CAM_CC_MCLK0_CLK_SRC 35 48#define CAM_CC_MCLK1_CLK 36 49#define CAM_CC_MCLK1_CLK_SRC 37 50#define CAM_CC_MCLK2_CLK 38 51#define CAM_CC_MCLK2_CLK_SRC 39 52#define CAM_CC_MCLK3_CLK 40 53#define CAM_CC_MCLK3_CLK_SRC 41 54#define CAM_CC_OPE_0_AHB_CLK 42 55#define CAM_CC_OPE_0_AREG_CLK 43 56#define CAM_CC_OPE_0_CLK 44 57#define CAM_CC_OPE_0_CLK_SRC 45 58#define CAM_CC_PLL0 46 59#define CAM_CC_PLL0_OUT_EVEN 47 60#define CAM_CC_PLL0_OUT_ODD 48 61#define CAM_CC_PLL1 49 62#define CAM_CC_PLL1_OUT_EVEN 50 63#define CAM_CC_PLL2 51 64#define CAM_CC_PLL2_OUT_EVEN 52 65#define CAM_CC_PLL3 53 66#define CAM_CC_PLL3_OUT_EVEN 54 67#define CAM_CC_PLL4 55 68#define CAM_CC_PLL4_OUT_EVEN 56 69#define CAM_CC_SLOW_AHB_CLK_SRC 57 70#define CAM_CC_SOC_AHB_CLK 58 71#define CAM_CC_SYS_TMR_CLK 59 72#define CAM_CC_TFE_0_AHB_CLK 60 73#define CAM_CC_TFE_0_CLK 61 74#define CAM_CC_TFE_0_CLK_SRC 62 75#define CAM_CC_TFE_0_CPHY_RX_CLK 63 76#define CAM_CC_TFE_0_CSID_CLK 64 77#define CAM_CC_TFE_0_CSID_CLK_SRC 65 78#define CAM_CC_TFE_1_AHB_CLK 66 79#define CAM_CC_TFE_1_CLK 67 80#define CAM_CC_TFE_1_CLK_SRC 68 81#define CAM_CC_TFE_1_CPHY_RX_CLK 69 82#define CAM_CC_TFE_1_CSID_CLK 70 83#define CAM_CC_TFE_1_CSID_CLK_SRC 71 84 85/* CAM_CC power domains */ 86#define CAM_CC_CAMSS_TOP_GDSC 0 87 88/* CAM_CC resets */ 89#define CAM_CC_BPS_BCR 0 90#define CAM_CC_CAMNOC_BCR 1 91#define CAM_CC_CAMSS_TOP_BCR 2 92#define CAM_CC_CCI_0_BCR 3 93#define CAM_CC_CCI_1_BCR 4 94#define CAM_CC_CPAS_BCR 5 95#define CAM_CC_CRE_BCR 6 96#define CAM_CC_CSI0PHY_BCR 7 97#define CAM_CC_CSI1PHY_BCR 8 98#define CAM_CC_CSI2PHY_BCR 9 99#define CAM_CC_ICP_BCR 10 100#define CAM_CC_MCLK0_BCR 11 101#define CAM_CC_MCLK1_BCR 12 102#define CAM_CC_MCLK2_BCR 13 103#define CAM_CC_MCLK3_BCR 14 104#define CAM_CC_OPE_0_BCR 15 105#define CAM_CC_TFE_0_BCR 16 106#define CAM_CC_TFE_1_BCR 17 107 108#endif 109