1/* $NetBSD: qcom,sm4450-dispcc.h,v 1.1.1.1 2026/01/18 05:21:36 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 6 */ 7 8#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H 9#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM4450_H 10 11/* DISP_CC clocks */ 12#define DISP_CC_MDSS_AHB1_CLK 0 13#define DISP_CC_MDSS_AHB_CLK 1 14#define DISP_CC_MDSS_AHB_CLK_SRC 2 15#define DISP_CC_MDSS_BYTE0_CLK 3 16#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 17#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 18#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 19#define DISP_CC_MDSS_ESC0_CLK 7 20#define DISP_CC_MDSS_ESC0_CLK_SRC 8 21#define DISP_CC_MDSS_MDP1_CLK 9 22#define DISP_CC_MDSS_MDP_CLK 10 23#define DISP_CC_MDSS_MDP_CLK_SRC 11 24#define DISP_CC_MDSS_MDP_LUT1_CLK 12 25#define DISP_CC_MDSS_MDP_LUT_CLK 13 26#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 14 27#define DISP_CC_MDSS_PCLK0_CLK 15 28#define DISP_CC_MDSS_PCLK0_CLK_SRC 16 29#define DISP_CC_MDSS_ROT1_CLK 17 30#define DISP_CC_MDSS_ROT_CLK 18 31#define DISP_CC_MDSS_ROT_CLK_SRC 19 32#define DISP_CC_MDSS_RSCC_AHB_CLK 20 33#define DISP_CC_MDSS_RSCC_VSYNC_CLK 21 34#define DISP_CC_MDSS_VSYNC1_CLK 22 35#define DISP_CC_MDSS_VSYNC_CLK 23 36#define DISP_CC_MDSS_VSYNC_CLK_SRC 24 37#define DISP_CC_PLL0 25 38#define DISP_CC_PLL1 26 39#define DISP_CC_SLEEP_CLK 27 40#define DISP_CC_SLEEP_CLK_SRC 28 41#define DISP_CC_XO_CLK 29 42#define DISP_CC_XO_CLK_SRC 30 43 44/* DISP_CC power domains */ 45#define DISP_CC_MDSS_CORE_GDSC 0 46#define DISP_CC_MDSS_CORE_INT2_GDSC 1 47 48/* DISP_CC resets */ 49#define DISP_CC_MDSS_CORE_BCR 0 50#define DISP_CC_MDSS_CORE_INT2_BCR 1 51#define DISP_CC_MDSS_RSCC_BCR 2 52 53#endif 54