1/* $NetBSD: qcom,sm6375-gcc.h,v 1.1.1.1 2026/01/18 05:21:37 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only */ 4/* 5 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022, Konrad Dybcio <konrad.dybcio@somainline.org> 7 */ 8 9#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H 10#define _DT_BINDINGS_CLK_QCOM_GCC_SM6375_H 11 12/* Clocks */ 13#define GPLL0 0 14#define GPLL0_OUT_EVEN 1 15#define GPLL0_OUT_ODD 2 16#define GPLL1 3 17#define GPLL10 4 18#define GPLL11 5 19#define GPLL3 6 20#define GPLL3_OUT_EVEN 7 21#define GPLL4 8 22#define GPLL5 9 23#define GPLL6 10 24#define GPLL6_OUT_EVEN 11 25#define GPLL7 12 26#define GPLL8 13 27#define GPLL8_OUT_EVEN 14 28#define GPLL9 15 29#define GPLL9_OUT_MAIN 16 30#define GCC_AHB2PHY_CSI_CLK 17 31#define GCC_AHB2PHY_USB_CLK 18 32#define GCC_BIMC_GPU_AXI_CLK 19 33#define GCC_BOOT_ROM_AHB_CLK 20 34#define GCC_CAM_THROTTLE_NRT_CLK 21 35#define GCC_CAM_THROTTLE_RT_CLK 22 36#define GCC_CAMERA_AHB_CLK 23 37#define GCC_CAMERA_XO_CLK 24 38#define GCC_CAMSS_AXI_CLK 25 39#define GCC_CAMSS_AXI_CLK_SRC 26 40#define GCC_CAMSS_CAMNOC_ATB_CLK 27 41#define GCC_CAMSS_CAMNOC_NTS_XO_CLK 28 42#define GCC_CAMSS_CCI_0_CLK 29 43#define GCC_CAMSS_CCI_0_CLK_SRC 30 44#define GCC_CAMSS_CCI_1_CLK 31 45#define GCC_CAMSS_CCI_1_CLK_SRC 32 46#define GCC_CAMSS_CPHY_0_CLK 33 47#define GCC_CAMSS_CPHY_1_CLK 34 48#define GCC_CAMSS_CPHY_2_CLK 35 49#define GCC_CAMSS_CPHY_3_CLK 36 50#define GCC_CAMSS_CSI0PHYTIMER_CLK 37 51#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 38 52#define GCC_CAMSS_CSI1PHYTIMER_CLK 39 53#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 40 54#define GCC_CAMSS_CSI2PHYTIMER_CLK 41 55#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 42 56#define GCC_CAMSS_CSI3PHYTIMER_CLK 43 57#define GCC_CAMSS_CSI3PHYTIMER_CLK_SRC 44 58#define GCC_CAMSS_MCLK0_CLK 45 59#define GCC_CAMSS_MCLK0_CLK_SRC 46 60#define GCC_CAMSS_MCLK1_CLK 47 61#define GCC_CAMSS_MCLK1_CLK_SRC 48 62#define GCC_CAMSS_MCLK2_CLK 49 63#define GCC_CAMSS_MCLK2_CLK_SRC 50 64#define GCC_CAMSS_MCLK3_CLK 51 65#define GCC_CAMSS_MCLK3_CLK_SRC 52 66#define GCC_CAMSS_MCLK4_CLK 53 67#define GCC_CAMSS_MCLK4_CLK_SRC 54 68#define GCC_CAMSS_NRT_AXI_CLK 55 69#define GCC_CAMSS_OPE_AHB_CLK 56 70#define GCC_CAMSS_OPE_AHB_CLK_SRC 57 71#define GCC_CAMSS_OPE_CLK 58 72#define GCC_CAMSS_OPE_CLK_SRC 59 73#define GCC_CAMSS_RT_AXI_CLK 60 74#define GCC_CAMSS_TFE_0_CLK 61 75#define GCC_CAMSS_TFE_0_CLK_SRC 62 76#define GCC_CAMSS_TFE_0_CPHY_RX_CLK 63 77#define GCC_CAMSS_TFE_0_CSID_CLK 64 78#define GCC_CAMSS_TFE_0_CSID_CLK_SRC 65 79#define GCC_CAMSS_TFE_1_CLK 66 80#define GCC_CAMSS_TFE_1_CLK_SRC 67 81#define GCC_CAMSS_TFE_1_CPHY_RX_CLK 68 82#define GCC_CAMSS_TFE_1_CSID_CLK 69 83#define GCC_CAMSS_TFE_1_CSID_CLK_SRC 70 84#define GCC_CAMSS_TFE_2_CLK 71 85#define GCC_CAMSS_TFE_2_CLK_SRC 72 86#define GCC_CAMSS_TFE_2_CPHY_RX_CLK 73 87#define GCC_CAMSS_TFE_2_CSID_CLK 74 88#define GCC_CAMSS_TFE_2_CSID_CLK_SRC 75 89#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC 76 90#define GCC_CAMSS_TOP_AHB_CLK 77 91#define GCC_CAMSS_TOP_AHB_CLK_SRC 78 92#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 79 93#define GCC_CPUSS_AHB_CLK_SRC 80 94#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 81 95#define GCC_CPUSS_GNOC_CLK 82 96#define GCC_DISP_AHB_CLK 83 97#define GCC_DISP_GPLL0_CLK_SRC 84 98#define GCC_DISP_GPLL0_DIV_CLK_SRC 85 99#define GCC_DISP_HF_AXI_CLK 86 100#define GCC_DISP_SLEEP_CLK 87 101#define GCC_DISP_THROTTLE_CORE_CLK 88 102#define GCC_DISP_XO_CLK 89 103#define GCC_GP1_CLK 90 104#define GCC_GP1_CLK_SRC 91 105#define GCC_GP2_CLK 92 106#define GCC_GP2_CLK_SRC 93 107#define GCC_GP3_CLK 94 108#define GCC_GP3_CLK_SRC 95 109#define GCC_GPU_CFG_AHB_CLK 96 110#define GCC_GPU_GPLL0_CLK_SRC 97 111#define GCC_GPU_GPLL0_DIV_CLK_SRC 98 112#define GCC_GPU_MEMNOC_GFX_CLK 99 113#define GCC_GPU_SNOC_DVM_GFX_CLK 100 114#define GCC_GPU_THROTTLE_CORE_CLK 101 115#define GCC_PDM2_CLK 102 116#define GCC_PDM2_CLK_SRC 103 117#define GCC_PDM_AHB_CLK 104 118#define GCC_PDM_XO4_CLK 105 119#define GCC_PRNG_AHB_CLK 106 120#define GCC_QMIP_CAMERA_NRT_AHB_CLK 107 121#define GCC_QMIP_CAMERA_RT_AHB_CLK 108 122#define GCC_QMIP_DISP_AHB_CLK 109 123#define GCC_QMIP_GPU_CFG_AHB_CLK 110 124#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 111 125#define GCC_QUPV3_WRAP0_CORE_2X_CLK 112 126#define GCC_QUPV3_WRAP0_CORE_CLK 113 127#define GCC_QUPV3_WRAP0_S0_CLK 114 128#define GCC_QUPV3_WRAP0_S0_CLK_SRC 115 129#define GCC_QUPV3_WRAP0_S1_CLK 116 130#define GCC_QUPV3_WRAP0_S1_CLK_SRC 117 131#define GCC_QUPV3_WRAP0_S2_CLK 118 132#define GCC_QUPV3_WRAP0_S2_CLK_SRC 119 133#define GCC_QUPV3_WRAP0_S3_CLK 120 134#define GCC_QUPV3_WRAP0_S3_CLK_SRC 121 135#define GCC_QUPV3_WRAP0_S4_CLK 122 136#define GCC_QUPV3_WRAP0_S4_CLK_SRC 123 137#define GCC_QUPV3_WRAP0_S5_CLK 124 138#define GCC_QUPV3_WRAP0_S5_CLK_SRC 125 139#define GCC_QUPV3_WRAP1_CORE_2X_CLK 126 140#define GCC_QUPV3_WRAP1_CORE_CLK 127 141#define GCC_QUPV3_WRAP1_S0_CLK 128 142#define GCC_QUPV3_WRAP1_S0_CLK_SRC 129 143#define GCC_QUPV3_WRAP1_S1_CLK 130 144#define GCC_QUPV3_WRAP1_S1_CLK_SRC 131 145#define GCC_QUPV3_WRAP1_S2_CLK 132 146#define GCC_QUPV3_WRAP1_S2_CLK_SRC 133 147#define GCC_QUPV3_WRAP1_S3_CLK 134 148#define GCC_QUPV3_WRAP1_S3_CLK_SRC 135 149#define GCC_QUPV3_WRAP1_S4_CLK 136 150#define GCC_QUPV3_WRAP1_S4_CLK_SRC 137 151#define GCC_QUPV3_WRAP1_S5_CLK 138 152#define GCC_QUPV3_WRAP1_S5_CLK_SRC 139 153#define GCC_QUPV3_WRAP_0_M_AHB_CLK 140 154#define GCC_QUPV3_WRAP_0_S_AHB_CLK 141 155#define GCC_QUPV3_WRAP_1_M_AHB_CLK 142 156#define GCC_QUPV3_WRAP_1_S_AHB_CLK 143 157#define GCC_RX5_PCIE_CLKREF_EN_CLK 144 158#define GCC_SDCC1_AHB_CLK 145 159#define GCC_SDCC1_APPS_CLK 146 160#define GCC_SDCC1_APPS_CLK_SRC 147 161#define GCC_SDCC1_ICE_CORE_CLK 148 162#define GCC_SDCC1_ICE_CORE_CLK_SRC 149 163#define GCC_SDCC2_AHB_CLK 150 164#define GCC_SDCC2_APPS_CLK 151 165#define GCC_SDCC2_APPS_CLK_SRC 152 166#define GCC_SYS_NOC_CPUSS_AHB_CLK 153 167#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 154 168#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 155 169#define GCC_UFS_MEM_CLKREF_CLK 156 170#define GCC_UFS_PHY_AHB_CLK 157 171#define GCC_UFS_PHY_AXI_CLK 158 172#define GCC_UFS_PHY_AXI_CLK_SRC 159 173#define GCC_UFS_PHY_ICE_CORE_CLK 160 174#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 161 175#define GCC_UFS_PHY_PHY_AUX_CLK 162 176#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 163 177#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164 178#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 165 179#define GCC_UFS_PHY_UNIPRO_CORE_CLK 166 180#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 167 181#define GCC_USB30_PRIM_MASTER_CLK 168 182#define GCC_USB30_PRIM_MASTER_CLK_SRC 169 183#define GCC_USB30_PRIM_MOCK_UTMI_CLK 170 184#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 171 185#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 172 186#define GCC_USB30_PRIM_SLEEP_CLK 173 187#define GCC_USB3_PRIM_CLKREF_CLK 174 188#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 175 189#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 176 190#define GCC_USB3_PRIM_PHY_PIPE_CLK 177 191#define GCC_VCODEC0_AXI_CLK 178 192#define GCC_VENUS_AHB_CLK 179 193#define GCC_VENUS_CTL_AXI_CLK 180 194#define GCC_VIDEO_AHB_CLK 181 195#define GCC_VIDEO_AXI0_CLK 182 196#define GCC_VIDEO_THROTTLE_CORE_CLK 183 197#define GCC_VIDEO_VCODEC0_SYS_CLK 184 198#define GCC_VIDEO_VENUS_CLK_SRC 185 199#define GCC_VIDEO_VENUS_CTL_CLK 186 200#define GCC_VIDEO_XO_CLK 187 201 202/* Resets */ 203#define GCC_CAMSS_OPE_BCR 0 204#define GCC_CAMSS_TFE_BCR 1 205#define GCC_CAMSS_TOP_BCR 2 206#define GCC_GPU_BCR 3 207#define GCC_MMSS_BCR 4 208#define GCC_PDM_BCR 5 209#define GCC_PRNG_BCR 6 210#define GCC_QUPV3_WRAPPER_0_BCR 7 211#define GCC_QUPV3_WRAPPER_1_BCR 8 212#define GCC_QUSB2PHY_PRIM_BCR 9 213#define GCC_QUSB2PHY_SEC_BCR 10 214#define GCC_SDCC1_BCR 11 215#define GCC_SDCC2_BCR 12 216#define GCC_UFS_PHY_BCR 13 217#define GCC_USB30_PRIM_BCR 14 218#define GCC_USB_PHY_CFG_AHB2PHY_BCR 15 219#define GCC_VCODEC0_BCR 16 220#define GCC_VENUS_BCR 17 221#define GCC_VIDEO_INTERFACE_BCR 18 222#define GCC_USB3_DP_PHY_PRIM_BCR 19 223#define GCC_USB3_PHY_PRIM_SP0_BCR 20 224 225/* GDSCs */ 226#define USB30_PRIM_GDSC 0 227#define UFS_PHY_GDSC 1 228#define CAMSS_TOP_GDSC 2 229#define VENUS_GDSC 3 230#define VCODEC0_GDSC 4 231#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC 5 232#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC 6 233#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 7 234#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 8 235 236#endif 237