1/* $NetBSD: qcom,sm7150-dispcc.h,v 1.1.1.1 2026/01/18 05:21:37 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com> 7 * Copyright (c) 2024, David Wronek <david@mainlining.org> 8 */ 9 10#ifndef _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H 11#define _DT_BINDINGS_CLK_QCOM_DISPCC_SM7150_H 12 13/* DISPCC clock registers */ 14#define DISPCC_PLL0 0 15#define DISPCC_MDSS_AHB_CLK 1 16#define DISPCC_MDSS_AHB_CLK_SRC 2 17#define DISPCC_MDSS_BYTE0_CLK 3 18#define DISPCC_MDSS_BYTE0_CLK_SRC 4 19#define DISPCC_MDSS_BYTE0_DIV_CLK_SRC 5 20#define DISPCC_MDSS_BYTE0_INTF_CLK 6 21#define DISPCC_MDSS_BYTE1_CLK 7 22#define DISPCC_MDSS_BYTE1_CLK_SRC 8 23#define DISPCC_MDSS_BYTE1_DIV_CLK_SRC 9 24#define DISPCC_MDSS_BYTE1_INTF_CLK 10 25#define DISPCC_MDSS_DP_AUX_CLK 11 26#define DISPCC_MDSS_DP_AUX_CLK_SRC 12 27#define DISPCC_MDSS_DP_CRYPTO_CLK 13 28#define DISPCC_MDSS_DP_CRYPTO_CLK_SRC 14 29#define DISPCC_MDSS_DP_LINK_CLK 15 30#define DISPCC_MDSS_DP_LINK_CLK_SRC 16 31#define DISPCC_MDSS_DP_LINK_INTF_CLK 17 32#define DISPCC_MDSS_DP_PIXEL1_CLK 18 33#define DISPCC_MDSS_DP_PIXEL1_CLK_SRC 19 34#define DISPCC_MDSS_DP_PIXEL_CLK 20 35#define DISPCC_MDSS_DP_PIXEL_CLK_SRC 21 36#define DISPCC_MDSS_ESC0_CLK 22 37#define DISPCC_MDSS_ESC0_CLK_SRC 23 38#define DISPCC_MDSS_ESC1_CLK 24 39#define DISPCC_MDSS_ESC1_CLK_SRC 25 40#define DISPCC_MDSS_MDP_CLK 26 41#define DISPCC_MDSS_MDP_CLK_SRC 27 42#define DISPCC_MDSS_MDP_LUT_CLK 28 43#define DISPCC_MDSS_NON_GDSC_AHB_CLK 29 44#define DISPCC_MDSS_PCLK0_CLK 30 45#define DISPCC_MDSS_PCLK0_CLK_SRC 31 46#define DISPCC_MDSS_PCLK1_CLK 32 47#define DISPCC_MDSS_PCLK1_CLK_SRC 33 48#define DISPCC_MDSS_ROT_CLK 34 49#define DISPCC_MDSS_ROT_CLK_SRC 35 50#define DISPCC_MDSS_RSCC_AHB_CLK 36 51#define DISPCC_MDSS_RSCC_VSYNC_CLK 37 52#define DISPCC_MDSS_VSYNC_CLK 38 53#define DISPCC_MDSS_VSYNC_CLK_SRC 39 54#define DISPCC_XO_CLK_SRC 40 55#define DISPCC_SLEEP_CLK 41 56#define DISPCC_SLEEP_CLK_SRC 42 57 58/* DISPCC GDSCR */ 59#define MDSS_GDSC 0 60 61#endif 62