1 /* $NetBSD: qcom,gcc-ipq4019.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 /* Copyright (c) 2015 The Linux Foundation. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 */ 18 #ifndef __QCOM_CLK_IPQ4019_H__ 19 #define __QCOM_CLK_IPQ4019_H__ 20 21 #define GCC_DUMMY_CLK 0 22 #define AUDIO_CLK_SRC 1 23 #define BLSP1_QUP1_I2C_APPS_CLK_SRC 2 24 #define BLSP1_QUP1_SPI_APPS_CLK_SRC 3 25 #define BLSP1_QUP2_I2C_APPS_CLK_SRC 4 26 #define BLSP1_QUP2_SPI_APPS_CLK_SRC 5 27 #define BLSP1_UART1_APPS_CLK_SRC 6 28 #define BLSP1_UART2_APPS_CLK_SRC 7 29 #define GCC_USB3_MOCK_UTMI_CLK_SRC 8 30 #define GCC_APPS_CLK_SRC 9 31 #define GCC_APPS_AHB_CLK_SRC 10 32 #define GP1_CLK_SRC 11 33 #define GP2_CLK_SRC 12 34 #define GP3_CLK_SRC 13 35 #define SDCC1_APPS_CLK_SRC 14 36 #define FEPHY_125M_DLY_CLK_SRC 15 37 #define WCSS2G_CLK_SRC 16 38 #define WCSS5G_CLK_SRC 17 39 #define GCC_APSS_AHB_CLK 18 40 #define GCC_AUDIO_AHB_CLK 19 41 #define GCC_AUDIO_PWM_CLK 20 42 #define GCC_BLSP1_AHB_CLK 21 43 #define GCC_BLSP1_QUP1_I2C_APPS_CLK 22 44 #define GCC_BLSP1_QUP1_SPI_APPS_CLK 23 45 #define GCC_BLSP1_QUP2_I2C_APPS_CLK 24 46 #define GCC_BLSP1_QUP2_SPI_APPS_CLK 25 47 #define GCC_BLSP1_UART1_APPS_CLK 26 48 #define GCC_BLSP1_UART2_APPS_CLK 27 49 #define GCC_DCD_XO_CLK 28 50 #define GCC_GP1_CLK 29 51 #define GCC_GP2_CLK 30 52 #define GCC_GP3_CLK 31 53 #define GCC_BOOT_ROM_AHB_CLK 32 54 #define GCC_CRYPTO_AHB_CLK 33 55 #define GCC_CRYPTO_AXI_CLK 34 56 #define GCC_CRYPTO_CLK 35 57 #define GCC_ESS_CLK 36 58 #define GCC_IMEM_AXI_CLK 37 59 #define GCC_IMEM_CFG_AHB_CLK 38 60 #define GCC_PCIE_AHB_CLK 39 61 #define GCC_PCIE_AXI_M_CLK 40 62 #define GCC_PCIE_AXI_S_CLK 41 63 #define GCC_PCNOC_AHB_CLK 42 64 #define GCC_PRNG_AHB_CLK 43 65 #define GCC_QPIC_AHB_CLK 44 66 #define GCC_QPIC_CLK 45 67 #define GCC_SDCC1_AHB_CLK 46 68 #define GCC_SDCC1_APPS_CLK 47 69 #define GCC_SNOC_PCNOC_AHB_CLK 48 70 #define GCC_SYS_NOC_125M_CLK 49 71 #define GCC_SYS_NOC_AXI_CLK 50 72 #define GCC_TCSR_AHB_CLK 51 73 #define GCC_TLMM_AHB_CLK 52 74 #define GCC_USB2_MASTER_CLK 53 75 #define GCC_USB2_SLEEP_CLK 54 76 #define GCC_USB2_MOCK_UTMI_CLK 55 77 #define GCC_USB3_MASTER_CLK 56 78 #define GCC_USB3_SLEEP_CLK 57 79 #define GCC_USB3_MOCK_UTMI_CLK 58 80 #define GCC_WCSS2G_CLK 59 81 #define GCC_WCSS2G_REF_CLK 60 82 #define GCC_WCSS2G_RTC_CLK 61 83 #define GCC_WCSS5G_CLK 62 84 #define GCC_WCSS5G_REF_CLK 63 85 #define GCC_WCSS5G_RTC_CLK 64 86 #define GCC_APSS_DDRPLL_VCO 65 87 #define GCC_SDCC_PLLDIV_CLK 66 88 #define GCC_FEPLL_VCO 67 89 #define GCC_FEPLL125_CLK 68 90 #define GCC_FEPLL125DLY_CLK 69 91 #define GCC_FEPLL200_CLK 70 92 #define GCC_FEPLL500_CLK 71 93 #define GCC_FEPLL_WCSS2G_CLK 72 94 #define GCC_FEPLL_WCSS5G_CLK 73 95 #define GCC_APSS_CPU_PLLDIV_CLK 74 96 #define GCC_PCNOC_AHB_CLK_SRC 75 97 98 #define WIFI0_CPU_INIT_RESET 0 99 #define WIFI0_RADIO_SRIF_RESET 1 100 #define WIFI0_RADIO_WARM_RESET 2 101 #define WIFI0_RADIO_COLD_RESET 3 102 #define WIFI0_CORE_WARM_RESET 4 103 #define WIFI0_CORE_COLD_RESET 5 104 #define WIFI1_CPU_INIT_RESET 6 105 #define WIFI1_RADIO_SRIF_RESET 7 106 #define WIFI1_RADIO_WARM_RESET 8 107 #define WIFI1_RADIO_COLD_RESET 9 108 #define WIFI1_CORE_WARM_RESET 10 109 #define WIFI1_CORE_COLD_RESET 11 110 #define USB3_UNIPHY_PHY_ARES 12 111 #define USB3_HSPHY_POR_ARES 13 112 #define USB3_HSPHY_S_ARES 14 113 #define USB2_HSPHY_POR_ARES 15 114 #define USB2_HSPHY_S_ARES 16 115 #define PCIE_PHY_AHB_ARES 17 116 #define PCIE_AHB_ARES 18 117 #define PCIE_PWR_ARES 19 118 #define PCIE_PIPE_STICKY_ARES 20 119 #define PCIE_AXI_M_STICKY_ARES 21 120 #define PCIE_PHY_ARES 22 121 #define PCIE_PARF_XPU_ARES 23 122 #define PCIE_AXI_S_XPU_ARES 24 123 #define PCIE_AXI_M_VMIDMT_ARES 25 124 #define PCIE_PIPE_ARES 26 125 #define PCIE_AXI_S_ARES 27 126 #define PCIE_AXI_M_ARES 28 127 #define ESS_RESET 29 128 #define GCC_BLSP1_BCR 30 129 #define GCC_BLSP1_QUP1_BCR 31 130 #define GCC_BLSP1_UART1_BCR 32 131 #define GCC_BLSP1_QUP2_BCR 33 132 #define GCC_BLSP1_UART2_BCR 34 133 #define GCC_BIMC_BCR 35 134 #define GCC_TLMM_BCR 36 135 #define GCC_IMEM_BCR 37 136 #define GCC_ESS_BCR 38 137 #define GCC_PRNG_BCR 39 138 #define GCC_BOOT_ROM_BCR 40 139 #define GCC_CRYPTO_BCR 41 140 #define GCC_SDCC1_BCR 42 141 #define GCC_SEC_CTRL_BCR 43 142 #define GCC_AUDIO_BCR 44 143 #define GCC_QPIC_BCR 45 144 #define GCC_PCIE_BCR 46 145 #define GCC_USB2_BCR 47 146 #define GCC_USB2_PHY_BCR 48 147 #define GCC_USB3_BCR 49 148 #define GCC_USB3_PHY_BCR 50 149 #define GCC_SYSTEM_NOC_BCR 51 150 #define GCC_PCNOC_BCR 52 151 #define GCC_DCD_BCR 53 152 #define GCC_SNOC_BUS_TIMEOUT0_BCR 54 153 #define GCC_SNOC_BUS_TIMEOUT1_BCR 55 154 #define GCC_SNOC_BUS_TIMEOUT2_BCR 56 155 #define GCC_SNOC_BUS_TIMEOUT3_BCR 57 156 #define GCC_PCNOC_BUS_TIMEOUT0_BCR 58 157 #define GCC_PCNOC_BUS_TIMEOUT1_BCR 59 158 #define GCC_PCNOC_BUS_TIMEOUT2_BCR 60 159 #define GCC_PCNOC_BUS_TIMEOUT3_BCR 61 160 #define GCC_PCNOC_BUS_TIMEOUT4_BCR 62 161 #define GCC_PCNOC_BUS_TIMEOUT5_BCR 63 162 #define GCC_PCNOC_BUS_TIMEOUT6_BCR 64 163 #define GCC_PCNOC_BUS_TIMEOUT7_BCR 65 164 #define GCC_PCNOC_BUS_TIMEOUT8_BCR 66 165 #define GCC_PCNOC_BUS_TIMEOUT9_BCR 67 166 #define GCC_TCSR_BCR 68 167 #define GCC_QDSS_BCR 69 168 #define GCC_MPM_BCR 70 169 #define GCC_SPDM_BCR 71 170 171 #endif 172
Indexes created Sun Sep 28 07:09:56 GMT 2025