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      1 /*	$NetBSD: qcom,gcc-ipq8074.h,v 1.1.1.4 2021/11/07 16:49:59 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only */
      4 /*
      5  * Copyright (c) 2016-2017, The Linux Foundation. All rights reserved.
      6  */
      7 
      8 #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
      9 #define _DT_BINDINGS_CLOCK_IPQ_GCC_8074_H
     10 
     11 #define GPLL0					0
     12 #define GPLL0_MAIN				1
     13 #define GCC_SLEEP_CLK_SRC			2
     14 #define BLSP1_QUP1_I2C_APPS_CLK_SRC		3
     15 #define BLSP1_QUP1_SPI_APPS_CLK_SRC		4
     16 #define BLSP1_QUP2_I2C_APPS_CLK_SRC		5
     17 #define BLSP1_QUP2_SPI_APPS_CLK_SRC		6
     18 #define BLSP1_QUP3_I2C_APPS_CLK_SRC		7
     19 #define BLSP1_QUP3_SPI_APPS_CLK_SRC		8
     20 #define BLSP1_QUP4_I2C_APPS_CLK_SRC		9
     21 #define BLSP1_QUP4_SPI_APPS_CLK_SRC		10
     22 #define BLSP1_QUP5_I2C_APPS_CLK_SRC		11
     23 #define BLSP1_QUP5_SPI_APPS_CLK_SRC		12
     24 #define BLSP1_QUP6_I2C_APPS_CLK_SRC		13
     25 #define BLSP1_QUP6_SPI_APPS_CLK_SRC		14
     26 #define BLSP1_UART1_APPS_CLK_SRC		15
     27 #define BLSP1_UART2_APPS_CLK_SRC		16
     28 #define BLSP1_UART3_APPS_CLK_SRC		17
     29 #define BLSP1_UART4_APPS_CLK_SRC		18
     30 #define BLSP1_UART5_APPS_CLK_SRC		19
     31 #define BLSP1_UART6_APPS_CLK_SRC		20
     32 #define GCC_BLSP1_AHB_CLK			21
     33 #define GCC_BLSP1_QUP1_I2C_APPS_CLK		22
     34 #define GCC_BLSP1_QUP1_SPI_APPS_CLK		23
     35 #define GCC_BLSP1_QUP2_I2C_APPS_CLK		24
     36 #define GCC_BLSP1_QUP2_SPI_APPS_CLK		25
     37 #define GCC_BLSP1_QUP3_I2C_APPS_CLK		26
     38 #define GCC_BLSP1_QUP3_SPI_APPS_CLK		27
     39 #define GCC_BLSP1_QUP4_I2C_APPS_CLK		28
     40 #define GCC_BLSP1_QUP4_SPI_APPS_CLK		29
     41 #define GCC_BLSP1_QUP5_I2C_APPS_CLK		30
     42 #define GCC_BLSP1_QUP5_SPI_APPS_CLK		31
     43 #define GCC_BLSP1_QUP6_I2C_APPS_CLK		32
     44 #define GCC_BLSP1_QUP6_SPI_APPS_CLK		33
     45 #define GCC_BLSP1_UART1_APPS_CLK		34
     46 #define GCC_BLSP1_UART2_APPS_CLK		35
     47 #define GCC_BLSP1_UART3_APPS_CLK		36
     48 #define GCC_BLSP1_UART4_APPS_CLK		37
     49 #define GCC_BLSP1_UART5_APPS_CLK		38
     50 #define GCC_BLSP1_UART6_APPS_CLK		39
     51 #define GCC_PRNG_AHB_CLK			40
     52 #define GCC_QPIC_AHB_CLK			41
     53 #define GCC_QPIC_CLK				42
     54 #define PCNOC_BFDCD_CLK_SRC			43
     55 #define GPLL2_MAIN				44
     56 #define GPLL2					45
     57 #define GPLL4_MAIN				46
     58 #define GPLL4					47
     59 #define GPLL6_MAIN				48
     60 #define GPLL6					49
     61 #define UBI32_PLL_MAIN				50
     62 #define UBI32_PLL				51
     63 #define NSS_CRYPTO_PLL_MAIN			52
     64 #define NSS_CRYPTO_PLL				53
     65 #define PCIE0_AXI_CLK_SRC			54
     66 #define PCIE0_AUX_CLK_SRC			55
     67 #define PCIE0_PIPE_CLK_SRC			56
     68 #define PCIE1_AXI_CLK_SRC			57
     69 #define PCIE1_AUX_CLK_SRC			58
     70 #define PCIE1_PIPE_CLK_SRC			59
     71 #define SDCC1_APPS_CLK_SRC			60
     72 #define SDCC1_ICE_CORE_CLK_SRC			61
     73 #define SDCC2_APPS_CLK_SRC			62
     74 #define USB0_MASTER_CLK_SRC			63
     75 #define USB0_AUX_CLK_SRC			64
     76 #define USB0_MOCK_UTMI_CLK_SRC			65
     77 #define USB0_PIPE_CLK_SRC			66
     78 #define USB1_MASTER_CLK_SRC			67
     79 #define USB1_AUX_CLK_SRC			68
     80 #define USB1_MOCK_UTMI_CLK_SRC			69
     81 #define USB1_PIPE_CLK_SRC			70
     82 #define GCC_XO_CLK_SRC				71
     83 #define SYSTEM_NOC_BFDCD_CLK_SRC		72
     84 #define NSS_CE_CLK_SRC				73
     85 #define NSS_NOC_BFDCD_CLK_SRC			74
     86 #define NSS_CRYPTO_CLK_SRC			75
     87 #define NSS_UBI0_CLK_SRC			76
     88 #define NSS_UBI0_DIV_CLK_SRC			77
     89 #define NSS_UBI1_CLK_SRC			78
     90 #define NSS_UBI1_DIV_CLK_SRC			79
     91 #define UBI_MPT_CLK_SRC				80
     92 #define NSS_IMEM_CLK_SRC			81
     93 #define NSS_PPE_CLK_SRC				82
     94 #define NSS_PORT1_RX_CLK_SRC			83
     95 #define NSS_PORT1_RX_DIV_CLK_SRC		84
     96 #define NSS_PORT1_TX_CLK_SRC			85
     97 #define NSS_PORT1_TX_DIV_CLK_SRC		86
     98 #define NSS_PORT2_RX_CLK_SRC			87
     99 #define NSS_PORT2_RX_DIV_CLK_SRC		88
    100 #define NSS_PORT2_TX_CLK_SRC			89
    101 #define NSS_PORT2_TX_DIV_CLK_SRC		90
    102 #define NSS_PORT3_RX_CLK_SRC			91
    103 #define NSS_PORT3_RX_DIV_CLK_SRC		92
    104 #define NSS_PORT3_TX_CLK_SRC			93
    105 #define NSS_PORT3_TX_DIV_CLK_SRC		94
    106 #define NSS_PORT4_RX_CLK_SRC			95
    107 #define NSS_PORT4_RX_DIV_CLK_SRC		96
    108 #define NSS_PORT4_TX_CLK_SRC			97
    109 #define NSS_PORT4_TX_DIV_CLK_SRC		98
    110 #define NSS_PORT5_RX_CLK_SRC			99
    111 #define NSS_PORT5_RX_DIV_CLK_SRC		100
    112 #define NSS_PORT5_TX_CLK_SRC			101
    113 #define NSS_PORT5_TX_DIV_CLK_SRC		102
    114 #define NSS_PORT6_RX_CLK_SRC			103
    115 #define NSS_PORT6_RX_DIV_CLK_SRC		104
    116 #define NSS_PORT6_TX_CLK_SRC			105
    117 #define NSS_PORT6_TX_DIV_CLK_SRC		106
    118 #define CRYPTO_CLK_SRC				107
    119 #define GP1_CLK_SRC				108
    120 #define GP2_CLK_SRC				109
    121 #define GP3_CLK_SRC				110
    122 #define GCC_PCIE0_AHB_CLK			111
    123 #define GCC_PCIE0_AUX_CLK			112
    124 #define GCC_PCIE0_AXI_M_CLK			113
    125 #define GCC_PCIE0_AXI_S_CLK			114
    126 #define GCC_PCIE0_PIPE_CLK			115
    127 #define GCC_SYS_NOC_PCIE0_AXI_CLK		116
    128 #define GCC_PCIE1_AHB_CLK			117
    129 #define GCC_PCIE1_AUX_CLK			118
    130 #define GCC_PCIE1_AXI_M_CLK			119
    131 #define GCC_PCIE1_AXI_S_CLK			120
    132 #define GCC_PCIE1_PIPE_CLK			121
    133 #define GCC_SYS_NOC_PCIE1_AXI_CLK		122
    134 #define GCC_USB0_AUX_CLK			123
    135 #define GCC_SYS_NOC_USB0_AXI_CLK		124
    136 #define GCC_USB0_MASTER_CLK			125
    137 #define GCC_USB0_MOCK_UTMI_CLK			126
    138 #define GCC_USB0_PHY_CFG_AHB_CLK		127
    139 #define GCC_USB0_PIPE_CLK			128
    140 #define GCC_USB0_SLEEP_CLK			129
    141 #define GCC_USB1_AUX_CLK			130
    142 #define GCC_SYS_NOC_USB1_AXI_CLK		131
    143 #define GCC_USB1_MASTER_CLK			132
    144 #define GCC_USB1_MOCK_UTMI_CLK			133
    145 #define GCC_USB1_PHY_CFG_AHB_CLK		134
    146 #define GCC_USB1_PIPE_CLK			135
    147 #define GCC_USB1_SLEEP_CLK			136
    148 #define GCC_SDCC1_AHB_CLK			137
    149 #define GCC_SDCC1_APPS_CLK			138
    150 #define GCC_SDCC1_ICE_CORE_CLK			139
    151 #define GCC_SDCC2_AHB_CLK			140
    152 #define GCC_SDCC2_APPS_CLK			141
    153 #define GCC_MEM_NOC_NSS_AXI_CLK			142
    154 #define GCC_NSS_CE_APB_CLK			143
    155 #define GCC_NSS_CE_AXI_CLK			144
    156 #define GCC_NSS_CFG_CLK				145
    157 #define GCC_NSS_CRYPTO_CLK			146
    158 #define GCC_NSS_CSR_CLK				147
    159 #define GCC_NSS_EDMA_CFG_CLK			148
    160 #define GCC_NSS_EDMA_CLK			149
    161 #define GCC_NSS_IMEM_CLK			150
    162 #define GCC_NSS_NOC_CLK				151
    163 #define GCC_NSS_PPE_BTQ_CLK			152
    164 #define GCC_NSS_PPE_CFG_CLK			153
    165 #define GCC_NSS_PPE_CLK				154
    166 #define GCC_NSS_PPE_IPE_CLK			155
    167 #define GCC_NSS_PTP_REF_CLK			156
    168 #define GCC_NSSNOC_CE_APB_CLK			157
    169 #define GCC_NSSNOC_CE_AXI_CLK			158
    170 #define GCC_NSSNOC_CRYPTO_CLK			159
    171 #define GCC_NSSNOC_PPE_CFG_CLK			160
    172 #define GCC_NSSNOC_PPE_CLK			161
    173 #define GCC_NSSNOC_QOSGEN_REF_CLK		162
    174 #define GCC_NSSNOC_SNOC_CLK			163
    175 #define GCC_NSSNOC_TIMEOUT_REF_CLK		164
    176 #define GCC_NSSNOC_UBI0_AHB_CLK			165
    177 #define GCC_NSSNOC_UBI1_AHB_CLK			166
    178 #define GCC_UBI0_AHB_CLK			167
    179 #define GCC_UBI0_AXI_CLK			168
    180 #define GCC_UBI0_NC_AXI_CLK			169
    181 #define GCC_UBI0_CORE_CLK			170
    182 #define GCC_UBI0_MPT_CLK			171
    183 #define GCC_UBI1_AHB_CLK			172
    184 #define GCC_UBI1_AXI_CLK			173
    185 #define GCC_UBI1_NC_AXI_CLK			174
    186 #define GCC_UBI1_CORE_CLK			175
    187 #define GCC_UBI1_MPT_CLK			176
    188 #define GCC_CMN_12GPLL_AHB_CLK			177
    189 #define GCC_CMN_12GPLL_SYS_CLK			178
    190 #define GCC_MDIO_AHB_CLK			179
    191 #define GCC_UNIPHY0_AHB_CLK			180
    192 #define GCC_UNIPHY0_SYS_CLK			181
    193 #define GCC_UNIPHY1_AHB_CLK			182
    194 #define GCC_UNIPHY1_SYS_CLK			183
    195 #define GCC_UNIPHY2_AHB_CLK			184
    196 #define GCC_UNIPHY2_SYS_CLK			185
    197 #define GCC_NSS_PORT1_RX_CLK			186
    198 #define GCC_NSS_PORT1_TX_CLK			187
    199 #define GCC_NSS_PORT2_RX_CLK			188
    200 #define GCC_NSS_PORT2_TX_CLK			189
    201 #define GCC_NSS_PORT3_RX_CLK			190
    202 #define GCC_NSS_PORT3_TX_CLK			191
    203 #define GCC_NSS_PORT4_RX_CLK			192
    204 #define GCC_NSS_PORT4_TX_CLK			193
    205 #define GCC_NSS_PORT5_RX_CLK			194
    206 #define GCC_NSS_PORT5_TX_CLK			195
    207 #define GCC_NSS_PORT6_RX_CLK			196
    208 #define GCC_NSS_PORT6_TX_CLK			197
    209 #define GCC_PORT1_MAC_CLK			198
    210 #define GCC_PORT2_MAC_CLK			199
    211 #define GCC_PORT3_MAC_CLK			200
    212 #define GCC_PORT4_MAC_CLK			201
    213 #define GCC_PORT5_MAC_CLK			202
    214 #define GCC_PORT6_MAC_CLK			203
    215 #define GCC_UNIPHY0_PORT1_RX_CLK		204
    216 #define GCC_UNIPHY0_PORT1_TX_CLK		205
    217 #define GCC_UNIPHY0_PORT2_RX_CLK		206
    218 #define GCC_UNIPHY0_PORT2_TX_CLK		207
    219 #define GCC_UNIPHY0_PORT3_RX_CLK		208
    220 #define GCC_UNIPHY0_PORT3_TX_CLK		209
    221 #define GCC_UNIPHY0_PORT4_RX_CLK		210
    222 #define GCC_UNIPHY0_PORT4_TX_CLK		211
    223 #define GCC_UNIPHY0_PORT5_RX_CLK		212
    224 #define GCC_UNIPHY0_PORT5_TX_CLK		213
    225 #define GCC_UNIPHY1_PORT5_RX_CLK		214
    226 #define GCC_UNIPHY1_PORT5_TX_CLK		215
    227 #define GCC_UNIPHY2_PORT6_RX_CLK		216
    228 #define GCC_UNIPHY2_PORT6_TX_CLK		217
    229 #define GCC_CRYPTO_AHB_CLK			218
    230 #define GCC_CRYPTO_AXI_CLK			219
    231 #define GCC_CRYPTO_CLK				220
    232 #define GCC_GP1_CLK				221
    233 #define GCC_GP2_CLK				222
    234 #define GCC_GP3_CLK				223
    235 #define GCC_PCIE0_AXI_S_BRIDGE_CLK		224
    236 #define GCC_PCIE0_RCHNG_CLK_SRC			225
    237 #define GCC_PCIE0_RCHNG_CLK			226
    238 
    239 #define GCC_BLSP1_BCR				0
    240 #define GCC_BLSP1_QUP1_BCR			1
    241 #define GCC_BLSP1_UART1_BCR			2
    242 #define GCC_BLSP1_QUP2_BCR			3
    243 #define GCC_BLSP1_UART2_BCR			4
    244 #define GCC_BLSP1_QUP3_BCR			5
    245 #define GCC_BLSP1_UART3_BCR			6
    246 #define GCC_BLSP1_QUP4_BCR			7
    247 #define GCC_BLSP1_UART4_BCR			8
    248 #define GCC_BLSP1_QUP5_BCR			9
    249 #define GCC_BLSP1_UART5_BCR			10
    250 #define GCC_BLSP1_QUP6_BCR			11
    251 #define GCC_BLSP1_UART6_BCR			12
    252 #define GCC_IMEM_BCR				13
    253 #define GCC_SMMU_BCR				14
    254 #define GCC_APSS_TCU_BCR			15
    255 #define GCC_SMMU_XPU_BCR			16
    256 #define GCC_PCNOC_TBU_BCR			17
    257 #define GCC_SMMU_CFG_BCR			18
    258 #define GCC_PRNG_BCR				19
    259 #define GCC_BOOT_ROM_BCR			20
    260 #define GCC_CRYPTO_BCR				21
    261 #define GCC_WCSS_BCR				22
    262 #define GCC_WCSS_Q6_BCR				23
    263 #define GCC_NSS_BCR				24
    264 #define GCC_SEC_CTRL_BCR			25
    265 #define GCC_ADSS_BCR				26
    266 #define GCC_DDRSS_BCR				27
    267 #define GCC_SYSTEM_NOC_BCR			28
    268 #define GCC_PCNOC_BCR				29
    269 #define GCC_TCSR_BCR				30
    270 #define GCC_QDSS_BCR				31
    271 #define GCC_DCD_BCR				32
    272 #define GCC_MSG_RAM_BCR				33
    273 #define GCC_MPM_BCR				34
    274 #define GCC_SPMI_BCR				35
    275 #define GCC_SPDM_BCR				36
    276 #define GCC_RBCPR_BCR				37
    277 #define GCC_RBCPR_MX_BCR			38
    278 #define GCC_TLMM_BCR				39
    279 #define GCC_RBCPR_WCSS_BCR			40
    280 #define GCC_USB0_PHY_BCR			41
    281 #define GCC_USB3PHY_0_PHY_BCR			42
    282 #define GCC_USB0_BCR				43
    283 #define GCC_USB1_PHY_BCR			44
    284 #define GCC_USB3PHY_1_PHY_BCR			45
    285 #define GCC_USB1_BCR				46
    286 #define GCC_QUSB2_0_PHY_BCR			47
    287 #define GCC_QUSB2_1_PHY_BCR			48
    288 #define GCC_SDCC1_BCR				49
    289 #define GCC_SDCC2_BCR				50
    290 #define GCC_SNOC_BUS_TIMEOUT0_BCR		51
    291 #define GCC_SNOC_BUS_TIMEOUT2_BCR		52
    292 #define GCC_SNOC_BUS_TIMEOUT3_BCR		53
    293 #define GCC_PCNOC_BUS_TIMEOUT0_BCR		54
    294 #define GCC_PCNOC_BUS_TIMEOUT1_BCR		55
    295 #define GCC_PCNOC_BUS_TIMEOUT2_BCR		56
    296 #define GCC_PCNOC_BUS_TIMEOUT3_BCR		57
    297 #define GCC_PCNOC_BUS_TIMEOUT4_BCR		58
    298 #define GCC_PCNOC_BUS_TIMEOUT5_BCR		59
    299 #define GCC_PCNOC_BUS_TIMEOUT6_BCR		60
    300 #define GCC_PCNOC_BUS_TIMEOUT7_BCR		61
    301 #define GCC_PCNOC_BUS_TIMEOUT8_BCR		62
    302 #define GCC_PCNOC_BUS_TIMEOUT9_BCR		63
    303 #define GCC_UNIPHY0_BCR				64
    304 #define GCC_UNIPHY1_BCR				65
    305 #define GCC_UNIPHY2_BCR				66
    306 #define GCC_CMN_12GPLL_BCR			67
    307 #define GCC_QPIC_BCR				68
    308 #define GCC_MDIO_BCR				69
    309 #define GCC_PCIE1_TBU_BCR			70
    310 #define GCC_WCSS_CORE_TBU_BCR			71
    311 #define GCC_WCSS_Q6_TBU_BCR			72
    312 #define GCC_USB0_TBU_BCR			73
    313 #define GCC_USB1_TBU_BCR			74
    314 #define GCC_PCIE0_TBU_BCR			75
    315 #define GCC_NSS_NOC_TBU_BCR			76
    316 #define GCC_PCIE0_BCR				77
    317 #define GCC_PCIE0_PHY_BCR			78
    318 #define GCC_PCIE0PHY_PHY_BCR			79
    319 #define GCC_PCIE0_LINK_DOWN_BCR			80
    320 #define GCC_PCIE1_BCR				81
    321 #define GCC_PCIE1_PHY_BCR			82
    322 #define GCC_PCIE1PHY_PHY_BCR			83
    323 #define GCC_PCIE1_LINK_DOWN_BCR			84
    324 #define GCC_DCC_BCR				85
    325 #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR	86
    326 #define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR	87
    327 #define GCC_SMMU_CATS_BCR			88
    328 #define GCC_UBI0_AXI_ARES			89
    329 #define GCC_UBI0_AHB_ARES			90
    330 #define GCC_UBI0_NC_AXI_ARES			91
    331 #define GCC_UBI0_DBG_ARES			92
    332 #define GCC_UBI0_CORE_CLAMP_ENABLE		93
    333 #define GCC_UBI0_CLKRST_CLAMP_ENABLE		94
    334 #define GCC_UBI1_AXI_ARES			95
    335 #define GCC_UBI1_AHB_ARES			96
    336 #define GCC_UBI1_NC_AXI_ARES			97
    337 #define GCC_UBI1_DBG_ARES			98
    338 #define GCC_UBI1_CORE_CLAMP_ENABLE		99
    339 #define GCC_UBI1_CLKRST_CLAMP_ENABLE		100
    340 #define GCC_NSS_CFG_ARES			101
    341 #define GCC_NSS_IMEM_ARES			102
    342 #define GCC_NSS_NOC_ARES			103
    343 #define GCC_NSS_CRYPTO_ARES			104
    344 #define GCC_NSS_CSR_ARES			105
    345 #define GCC_NSS_CE_APB_ARES			106
    346 #define GCC_NSS_CE_AXI_ARES			107
    347 #define GCC_NSSNOC_CE_APB_ARES			108
    348 #define GCC_NSSNOC_CE_AXI_ARES			109
    349 #define GCC_NSSNOC_UBI0_AHB_ARES		110
    350 #define GCC_NSSNOC_UBI1_AHB_ARES		111
    351 #define GCC_NSSNOC_SNOC_ARES			112
    352 #define GCC_NSSNOC_CRYPTO_ARES			113
    353 #define GCC_NSSNOC_ATB_ARES			114
    354 #define GCC_NSSNOC_QOSGEN_REF_ARES		115
    355 #define GCC_NSSNOC_TIMEOUT_REF_ARES		116
    356 #define GCC_PCIE0_PIPE_ARES			117
    357 #define GCC_PCIE0_SLEEP_ARES			118
    358 #define GCC_PCIE0_CORE_STICKY_ARES		119
    359 #define GCC_PCIE0_AXI_MASTER_ARES		120
    360 #define GCC_PCIE0_AXI_SLAVE_ARES		121
    361 #define GCC_PCIE0_AHB_ARES			122
    362 #define GCC_PCIE0_AXI_MASTER_STICKY_ARES	123
    363 #define GCC_PCIE1_PIPE_ARES			124
    364 #define GCC_PCIE1_SLEEP_ARES			125
    365 #define GCC_PCIE1_CORE_STICKY_ARES		126
    366 #define GCC_PCIE1_AXI_MASTER_ARES		127
    367 #define GCC_PCIE1_AXI_SLAVE_ARES		128
    368 #define GCC_PCIE1_AHB_ARES			129
    369 #define GCC_PCIE1_AXI_MASTER_STICKY_ARES	130
    370 #define GCC_PCIE0_AXI_SLAVE_STICKY_ARES		131
    371 
    372 #endif
    373