1 /* $NetBSD: qcom,gcc-msm8660.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2013, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8660_H 9 #define _DT_BINDINGS_CLK_MSM_GCC_8660_H 10 11 #define AFAB_CLK_SRC 0 12 #define AFAB_CORE_CLK 1 13 #define SCSS_A_CLK 2 14 #define SCSS_H_CLK 3 15 #define SCSS_XO_SRC_CLK 4 16 #define AFAB_EBI1_CH0_A_CLK 5 17 #define AFAB_EBI1_CH1_A_CLK 6 18 #define AFAB_AXI_S0_FCLK 7 19 #define AFAB_AXI_S1_FCLK 8 20 #define AFAB_AXI_S2_FCLK 9 21 #define AFAB_AXI_S3_FCLK 10 22 #define AFAB_AXI_S4_FCLK 11 23 #define SFAB_CORE_CLK 12 24 #define SFAB_AXI_S0_FCLK 13 25 #define SFAB_AXI_S1_FCLK 14 26 #define SFAB_AXI_S2_FCLK 15 27 #define SFAB_AXI_S3_FCLK 16 28 #define SFAB_AXI_S4_FCLK 17 29 #define SFAB_AHB_S0_FCLK 18 30 #define SFAB_AHB_S1_FCLK 19 31 #define SFAB_AHB_S2_FCLK 20 32 #define SFAB_AHB_S3_FCLK 21 33 #define SFAB_AHB_S4_FCLK 22 34 #define SFAB_AHB_S5_FCLK 23 35 #define SFAB_AHB_S6_FCLK 24 36 #define SFAB_ADM0_M0_A_CLK 25 37 #define SFAB_ADM0_M1_A_CLK 26 38 #define SFAB_ADM0_M2_A_CLK 27 39 #define ADM0_CLK 28 40 #define ADM0_PBUS_CLK 29 41 #define SFAB_ADM1_M0_A_CLK 30 42 #define SFAB_ADM1_M1_A_CLK 31 43 #define SFAB_ADM1_M2_A_CLK 32 44 #define MMFAB_ADM1_M3_A_CLK 33 45 #define ADM1_CLK 34 46 #define ADM1_PBUS_CLK 35 47 #define IMEM0_A_CLK 36 48 #define MAHB0_CLK 37 49 #define SFAB_LPASS_Q6_A_CLK 38 50 #define SFAB_AFAB_M_A_CLK 39 51 #define AFAB_SFAB_M0_A_CLK 40 52 #define AFAB_SFAB_M1_A_CLK 41 53 #define DFAB_CLK_SRC 42 54 #define DFAB_CLK 43 55 #define DFAB_CORE_CLK 44 56 #define SFAB_DFAB_M_A_CLK 45 57 #define DFAB_SFAB_M_A_CLK 46 58 #define DFAB_SWAY0_H_CLK 47 59 #define DFAB_SWAY1_H_CLK 48 60 #define DFAB_ARB0_H_CLK 49 61 #define DFAB_ARB1_H_CLK 50 62 #define PPSS_H_CLK 51 63 #define PPSS_PROC_CLK 52 64 #define PPSS_TIMER0_CLK 53 65 #define PPSS_TIMER1_CLK 54 66 #define PMEM_A_CLK 55 67 #define DMA_BAM_H_CLK 56 68 #define SIC_H_CLK 57 69 #define SPS_TIC_H_CLK 58 70 #define SLIMBUS_H_CLK 59 71 #define SLIMBUS_XO_SRC_CLK 60 72 #define CFPB_2X_CLK_SRC 61 73 #define CFPB_CLK 62 74 #define CFPB0_H_CLK 63 75 #define CFPB1_H_CLK 64 76 #define CFPB2_H_CLK 65 77 #define EBI2_2X_CLK 66 78 #define EBI2_CLK 67 79 #define SFAB_CFPB_M_H_CLK 68 80 #define CFPB_MASTER_H_CLK 69 81 #define SFAB_CFPB_S_HCLK 70 82 #define CFPB_SPLITTER_H_CLK 71 83 #define TSIF_H_CLK 72 84 #define TSIF_INACTIVITY_TIMERS_CLK 73 85 #define TSIF_REF_SRC 74 86 #define TSIF_REF_CLK 75 87 #define CE1_H_CLK 76 88 #define CE2_H_CLK 77 89 #define SFPB_H_CLK_SRC 78 90 #define SFPB_H_CLK 79 91 #define SFAB_SFPB_M_H_CLK 80 92 #define SFAB_SFPB_S_H_CLK 81 93 #define RPM_PROC_CLK 82 94 #define RPM_BUS_H_CLK 83 95 #define RPM_SLEEP_CLK 84 96 #define RPM_TIMER_CLK 85 97 #define MODEM_AHB1_H_CLK 86 98 #define MODEM_AHB2_H_CLK 87 99 #define RPM_MSG_RAM_H_CLK 88 100 #define SC_H_CLK 89 101 #define SC_A_CLK 90 102 #define PMIC_ARB0_H_CLK 91 103 #define PMIC_ARB1_H_CLK 92 104 #define PMIC_SSBI2_SRC 93 105 #define PMIC_SSBI2_CLK 94 106 #define SDC1_H_CLK 95 107 #define SDC2_H_CLK 96 108 #define SDC3_H_CLK 97 109 #define SDC4_H_CLK 98 110 #define SDC5_H_CLK 99 111 #define SDC1_SRC 100 112 #define SDC2_SRC 101 113 #define SDC3_SRC 102 114 #define SDC4_SRC 103 115 #define SDC5_SRC 104 116 #define SDC1_CLK 105 117 #define SDC2_CLK 106 118 #define SDC3_CLK 107 119 #define SDC4_CLK 108 120 #define SDC5_CLK 109 121 #define USB_HS1_H_CLK 110 122 #define USB_HS1_XCVR_SRC 111 123 #define USB_HS1_XCVR_CLK 112 124 #define USB_HS2_H_CLK 113 125 #define USB_HS2_XCVR_SRC 114 126 #define USB_HS2_XCVR_CLK 115 127 #define USB_FS1_H_CLK 116 128 #define USB_FS1_XCVR_FS_SRC 117 129 #define USB_FS1_XCVR_FS_CLK 118 130 #define USB_FS1_SYSTEM_CLK 119 131 #define USB_FS2_H_CLK 120 132 #define USB_FS2_XCVR_FS_SRC 121 133 #define USB_FS2_XCVR_FS_CLK 122 134 #define USB_FS2_SYSTEM_CLK 123 135 #define GSBI_COMMON_SIM_SRC 124 136 #define GSBI1_H_CLK 125 137 #define GSBI2_H_CLK 126 138 #define GSBI3_H_CLK 127 139 #define GSBI4_H_CLK 128 140 #define GSBI5_H_CLK 129 141 #define GSBI6_H_CLK 130 142 #define GSBI7_H_CLK 131 143 #define GSBI8_H_CLK 132 144 #define GSBI9_H_CLK 133 145 #define GSBI10_H_CLK 134 146 #define GSBI11_H_CLK 135 147 #define GSBI12_H_CLK 136 148 #define GSBI1_UART_SRC 137 149 #define GSBI1_UART_CLK 138 150 #define GSBI2_UART_SRC 139 151 #define GSBI2_UART_CLK 140 152 #define GSBI3_UART_SRC 141 153 #define GSBI3_UART_CLK 142 154 #define GSBI4_UART_SRC 143 155 #define GSBI4_UART_CLK 144 156 #define GSBI5_UART_SRC 145 157 #define GSBI5_UART_CLK 146 158 #define GSBI6_UART_SRC 147 159 #define GSBI6_UART_CLK 148 160 #define GSBI7_UART_SRC 149 161 #define GSBI7_UART_CLK 150 162 #define GSBI8_UART_SRC 151 163 #define GSBI8_UART_CLK 152 164 #define GSBI9_UART_SRC 153 165 #define GSBI9_UART_CLK 154 166 #define GSBI10_UART_SRC 155 167 #define GSBI10_UART_CLK 156 168 #define GSBI11_UART_SRC 157 169 #define GSBI11_UART_CLK 158 170 #define GSBI12_UART_SRC 159 171 #define GSBI12_UART_CLK 160 172 #define GSBI1_QUP_SRC 161 173 #define GSBI1_QUP_CLK 162 174 #define GSBI2_QUP_SRC 163 175 #define GSBI2_QUP_CLK 164 176 #define GSBI3_QUP_SRC 165 177 #define GSBI3_QUP_CLK 166 178 #define GSBI4_QUP_SRC 167 179 #define GSBI4_QUP_CLK 168 180 #define GSBI5_QUP_SRC 169 181 #define GSBI5_QUP_CLK 170 182 #define GSBI6_QUP_SRC 171 183 #define GSBI6_QUP_CLK 172 184 #define GSBI7_QUP_SRC 173 185 #define GSBI7_QUP_CLK 174 186 #define GSBI8_QUP_SRC 175 187 #define GSBI8_QUP_CLK 176 188 #define GSBI9_QUP_SRC 177 189 #define GSBI9_QUP_CLK 178 190 #define GSBI10_QUP_SRC 179 191 #define GSBI10_QUP_CLK 180 192 #define GSBI11_QUP_SRC 181 193 #define GSBI11_QUP_CLK 182 194 #define GSBI12_QUP_SRC 183 195 #define GSBI12_QUP_CLK 184 196 #define GSBI1_SIM_CLK 185 197 #define GSBI2_SIM_CLK 186 198 #define GSBI3_SIM_CLK 187 199 #define GSBI4_SIM_CLK 188 200 #define GSBI5_SIM_CLK 189 201 #define GSBI6_SIM_CLK 190 202 #define GSBI7_SIM_CLK 191 203 #define GSBI8_SIM_CLK 192 204 #define GSBI9_SIM_CLK 193 205 #define GSBI10_SIM_CLK 194 206 #define GSBI11_SIM_CLK 195 207 #define GSBI12_SIM_CLK 196 208 #define SPDM_CFG_H_CLK 197 209 #define SPDM_MSTR_H_CLK 198 210 #define SPDM_FF_CLK_SRC 199 211 #define SPDM_FF_CLK 200 212 #define SEC_CTRL_CLK 201 213 #define SEC_CTRL_ACC_CLK_SRC 202 214 #define SEC_CTRL_ACC_CLK 203 215 #define TLMM_H_CLK 204 216 #define TLMM_CLK 205 217 #define MARM_CLK_SRC 206 218 #define MARM_CLK 207 219 #define MAHB1_SRC 208 220 #define MAHB1_CLK 209 221 #define SFAB_MSS_S_H_CLK 210 222 #define MAHB2_SRC 211 223 #define MAHB2_CLK 212 224 #define MSS_MODEM_CLK_SRC 213 225 #define MSS_MODEM_CXO_CLK 214 226 #define MSS_SLP_CLK 215 227 #define MSS_SYS_REF_CLK 216 228 #define TSSC_CLK_SRC 217 229 #define TSSC_CLK 218 230 #define PDM_SRC 219 231 #define PDM_CLK 220 232 #define GP0_SRC 221 233 #define GP0_CLK 222 234 #define GP1_SRC 223 235 #define GP1_CLK 224 236 #define GP2_SRC 225 237 #define GP2_CLK 226 238 #define PMEM_CLK 227 239 #define MPM_CLK 228 240 #define EBI1_ASFAB_SRC 229 241 #define EBI1_CLK_SRC 230 242 #define EBI1_CH0_CLK 231 243 #define EBI1_CH1_CLK 232 244 #define SFAB_SMPSS_S_H_CLK 233 245 #define PRNG_SRC 234 246 #define PRNG_CLK 235 247 #define PXO_SRC 236 248 #define LPASS_CXO_CLK 237 249 #define LPASS_PXO_CLK 238 250 #define SPDM_CY_PORT0_CLK 239 251 #define SPDM_CY_PORT1_CLK 240 252 #define SPDM_CY_PORT2_CLK 241 253 #define SPDM_CY_PORT3_CLK 242 254 #define SPDM_CY_PORT4_CLK 243 255 #define SPDM_CY_PORT5_CLK 244 256 #define SPDM_CY_PORT6_CLK 245 257 #define SPDM_CY_PORT7_CLK 246 258 #define PLL0 247 259 #define PLL0_VOTE 248 260 #define PLL5 249 261 #define PLL6 250 262 #define PLL6_VOTE 251 263 #define PLL8 252 264 #define PLL8_VOTE 253 265 #define PLL9 254 266 #define PLL10 255 267 #define PLL11 256 268 #define PLL12 257 269 270 #endif 271
Indexes created Tue Sep 30 20:09:53 GMT 2025