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      1 /*	$NetBSD: qcom,gcc-msm8917.h,v 1.1.1.1 2026/01/18 05:21:35 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      4 
      5 #ifndef _DT_BINDINGS_CLK_MSM_GCC_8917_H
      6 #define _DT_BINDINGS_CLK_MSM_GCC_8917_H
      7 
      8 /* Clocks */
      9 #define APSS_AHB_CLK_SRC			0
     10 #define BLSP1_QUP2_I2C_APPS_CLK_SRC		1
     11 #define BLSP1_QUP2_SPI_APPS_CLK_SRC		2
     12 #define BLSP1_QUP3_I2C_APPS_CLK_SRC		3
     13 #define BLSP1_QUP3_SPI_APPS_CLK_SRC		4
     14 #define BLSP1_QUP4_I2C_APPS_CLK_SRC		5
     15 #define BLSP1_QUP4_SPI_APPS_CLK_SRC		6
     16 #define BLSP1_UART1_APPS_CLK_SRC		7
     17 #define BLSP1_UART2_APPS_CLK_SRC		8
     18 #define BLSP2_QUP1_I2C_APPS_CLK_SRC		9
     19 #define BLSP2_QUP1_SPI_APPS_CLK_SRC		10
     20 #define BLSP2_QUP2_I2C_APPS_CLK_SRC		11
     21 #define BLSP2_QUP2_SPI_APPS_CLK_SRC		12
     22 #define BLSP2_QUP3_I2C_APPS_CLK_SRC		13
     23 #define BLSP2_QUP3_SPI_APPS_CLK_SRC		14
     24 #define BLSP2_UART1_APPS_CLK_SRC		15
     25 #define BLSP2_UART2_APPS_CLK_SRC		16
     26 #define BYTE0_CLK_SRC				17
     27 #define CAMSS_GP0_CLK_SRC			18
     28 #define CAMSS_GP1_CLK_SRC			19
     29 #define CAMSS_TOP_AHB_CLK_SRC			20
     30 #define CCI_CLK_SRC				21
     31 #define CPP_CLK_SRC				22
     32 #define CRYPTO_CLK_SRC				23
     33 #define CSI0PHYTIMER_CLK_SRC			24
     34 #define CSI0_CLK_SRC				25
     35 #define CSI1PHYTIMER_CLK_SRC			26
     36 #define CSI1_CLK_SRC				27
     37 #define CSI2_CLK_SRC				28
     38 #define ESC0_CLK_SRC				29
     39 #define GCC_APSS_TCU_CLK			30
     40 #define GCC_BIMC_GFX_CLK			31
     41 #define GCC_BIMC_GPU_CLK			32
     42 #define GCC_BLSP1_AHB_CLK			33
     43 #define GCC_BLSP1_QUP2_I2C_APPS_CLK		34
     44 #define GCC_BLSP1_QUP2_SPI_APPS_CLK		35
     45 #define GCC_BLSP1_QUP3_I2C_APPS_CLK		36
     46 #define GCC_BLSP1_QUP3_SPI_APPS_CLK		37
     47 #define GCC_BLSP1_QUP4_I2C_APPS_CLK		38
     48 #define GCC_BLSP1_QUP4_SPI_APPS_CLK		39
     49 #define GCC_BLSP1_UART1_APPS_CLK		40
     50 #define GCC_BLSP1_UART2_APPS_CLK		41
     51 #define GCC_BLSP2_AHB_CLK			42
     52 #define GCC_BLSP2_QUP1_I2C_APPS_CLK		43
     53 #define GCC_BLSP2_QUP1_SPI_APPS_CLK		44
     54 #define GCC_BLSP2_QUP2_I2C_APPS_CLK		45
     55 #define GCC_BLSP2_QUP2_SPI_APPS_CLK		46
     56 #define GCC_BLSP2_QUP3_I2C_APPS_CLK		47
     57 #define GCC_BLSP2_QUP3_SPI_APPS_CLK		48
     58 #define GCC_BLSP2_UART1_APPS_CLK		49
     59 #define GCC_BLSP2_UART2_APPS_CLK		50
     60 #define GCC_BOOT_ROM_AHB_CLK			51
     61 #define GCC_CAMSS_AHB_CLK			52
     62 #define GCC_CAMSS_CCI_AHB_CLK			53
     63 #define GCC_CAMSS_CCI_CLK			54
     64 #define GCC_CAMSS_CPP_AHB_CLK			55
     65 #define GCC_CAMSS_CPP_CLK			56
     66 #define GCC_CAMSS_CSI0PHYTIMER_CLK		57
     67 #define GCC_CAMSS_CSI0PHY_CLK			58
     68 #define GCC_CAMSS_CSI0PIX_CLK			59
     69 #define GCC_CAMSS_CSI0RDI_CLK			60
     70 #define GCC_CAMSS_CSI0_AHB_CLK			61
     71 #define GCC_CAMSS_CSI0_CLK			62
     72 #define GCC_CAMSS_CSI1PHYTIMER_CLK		63
     73 #define GCC_CAMSS_CSI1PHY_CLK			64
     74 #define GCC_CAMSS_CSI1PIX_CLK			65
     75 #define GCC_CAMSS_CSI1RDI_CLK			66
     76 #define GCC_CAMSS_CSI1_AHB_CLK			67
     77 #define GCC_CAMSS_CSI1_CLK			68
     78 #define GCC_CAMSS_CSI2PHY_CLK			69
     79 #define GCC_CAMSS_CSI2PIX_CLK			70
     80 #define GCC_CAMSS_CSI2RDI_CLK			71
     81 #define GCC_CAMSS_CSI2_AHB_CLK			72
     82 #define GCC_CAMSS_CSI2_CLK			73
     83 #define GCC_CAMSS_CSI_VFE0_CLK			74
     84 #define GCC_CAMSS_CSI_VFE1_CLK			75
     85 #define GCC_CAMSS_GP0_CLK			76
     86 #define GCC_CAMSS_GP1_CLK			77
     87 #define GCC_CAMSS_ISPIF_AHB_CLK			78
     88 #define GCC_CAMSS_JPEG0_CLK			79
     89 #define GCC_CAMSS_JPEG_AHB_CLK			80
     90 #define GCC_CAMSS_JPEG_AXI_CLK			81
     91 #define GCC_CAMSS_MCLK0_CLK			82
     92 #define GCC_CAMSS_MCLK1_CLK			83
     93 #define GCC_CAMSS_MCLK2_CLK			84
     94 #define GCC_CAMSS_MICRO_AHB_CLK			85
     95 #define GCC_CAMSS_TOP_AHB_CLK			86
     96 #define GCC_CAMSS_VFE0_AHB_CLK			87
     97 #define GCC_CAMSS_VFE0_AXI_CLK			88
     98 #define GCC_CAMSS_VFE0_CLK			89
     99 #define GCC_CAMSS_VFE1_AHB_CLK			90
    100 #define GCC_CAMSS_VFE1_AXI_CLK			91
    101 #define GCC_CAMSS_VFE1_CLK			92
    102 #define GCC_CPP_TBU_CLK				93
    103 #define GCC_CRYPTO_AHB_CLK			94
    104 #define GCC_CRYPTO_AXI_CLK			95
    105 #define GCC_CRYPTO_CLK				96
    106 #define GCC_DCC_CLK				97
    107 #define GCC_GFX_TBU_CLK				98
    108 #define GCC_GFX_TCU_CLK				99
    109 #define GCC_GP1_CLK				100
    110 #define GCC_GP2_CLK				101
    111 #define GCC_GP3_CLK				102
    112 #define GCC_GTCU_AHB_CLK			103
    113 #define GCC_JPEG_TBU_CLK			104
    114 #define GCC_MDP_TBU_CLK				105
    115 #define GCC_MDSS_AHB_CLK			106
    116 #define GCC_MDSS_AXI_CLK			107
    117 #define GCC_MDSS_BYTE0_CLK			108
    118 #define GCC_MDSS_ESC0_CLK			109
    119 #define GCC_MDSS_MDP_CLK			110
    120 #define GCC_MDSS_PCLK0_CLK			111
    121 #define GCC_MDSS_VSYNC_CLK			112
    122 #define GCC_MSS_CFG_AHB_CLK			113
    123 #define GCC_MSS_Q6_BIMC_AXI_CLK			114
    124 #define GCC_OXILI_AHB_CLK			115
    125 #define GCC_OXILI_GFX3D_CLK			116
    126 #define GCC_PDM2_CLK				117
    127 #define GCC_PDM_AHB_CLK				118
    128 #define GCC_PRNG_AHB_CLK			119
    129 #define GCC_QDSS_DAP_CLK			120
    130 #define GCC_SDCC1_AHB_CLK			121
    131 #define GCC_SDCC1_APPS_CLK			122
    132 #define GCC_SDCC1_ICE_CORE_CLK			123
    133 #define GCC_SDCC2_AHB_CLK			124
    134 #define GCC_SDCC2_APPS_CLK			125
    135 #define GCC_SMMU_CFG_CLK			126
    136 #define GCC_USB2A_PHY_SLEEP_CLK			127
    137 #define GCC_USB_HS_AHB_CLK			128
    138 #define GCC_USB_HS_PHY_CFG_AHB_CLK		129
    139 #define GCC_USB_HS_SYSTEM_CLK			130
    140 #define GCC_VENUS0_AHB_CLK			131
    141 #define GCC_VENUS0_AXI_CLK			132
    142 #define GCC_VENUS0_CORE0_VCODEC0_CLK		133
    143 #define GCC_VENUS0_VCODEC0_CLK			134
    144 #define GCC_VENUS_TBU_CLK			135
    145 #define GCC_VFE1_TBU_CLK			136
    146 #define GCC_VFE_TBU_CLK				137
    147 #define GFX3D_CLK_SRC				138
    148 #define GP1_CLK_SRC				139
    149 #define GP2_CLK_SRC				140
    150 #define GP3_CLK_SRC				141
    151 #define GPLL0					142
    152 #define GPLL0_EARLY				143
    153 #define GPLL3					144
    154 #define GPLL3_EARLY				145
    155 #define GPLL4					146
    156 #define GPLL4_EARLY				147
    157 #define GPLL6					148
    158 #define GPLL6_EARLY				149
    159 #define JPEG0_CLK_SRC				150
    160 #define MCLK0_CLK_SRC				151
    161 #define MCLK1_CLK_SRC				152
    162 #define MCLK2_CLK_SRC				153
    163 #define MDP_CLK_SRC				154
    164 #define PCLK0_CLK_SRC				155
    165 #define PDM2_CLK_SRC				156
    166 #define SDCC1_APPS_CLK_SRC			157
    167 #define SDCC1_ICE_CORE_CLK_SRC			158
    168 #define SDCC2_APPS_CLK_SRC			159
    169 #define USB_HS_SYSTEM_CLK_SRC			160
    170 #define VCODEC0_CLK_SRC				161
    171 #define VFE0_CLK_SRC				162
    172 #define VFE1_CLK_SRC				163
    173 #define VSYNC_CLK_SRC				164
    174 #define GPLL0_SLEEP_CLK_SRC			165
    175 
    176 /* GCC block resets */
    177 #define GCC_CAMSS_MICRO_BCR			0
    178 #define GCC_MSS_BCR				1
    179 #define GCC_QUSB2_PHY_BCR			2
    180 #define GCC_USB_HS_BCR				3
    181 #define GCC_USB2_HS_PHY_ONLY_BCR		4
    182 
    183 /* GDSCs */
    184 #define CPP_GDSC				0
    185 #define JPEG_GDSC				1
    186 #define MDSS_GDSC				2
    187 #define OXILI_GX_GDSC				3
    188 #define VENUS_CORE0_GDSC			4
    189 #define VENUS_GDSC				5
    190 #define VFE0_GDSC				6
    191 #define VFE1_GDSC				7
    192 
    193 #endif
    194