1 /* $NetBSD: qcom,gcc-sc7280.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4 /* 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H 9 #define _DT_BINDINGS_CLK_QCOM_GCC_SC7280_H 10 11 /* GCC clocks */ 12 #define GCC_GPLL0 0 13 #define GCC_GPLL0_OUT_EVEN 1 14 #define GCC_GPLL0_OUT_ODD 2 15 #define GCC_GPLL1 3 16 #define GCC_GPLL10 4 17 #define GCC_GPLL4 5 18 #define GCC_GPLL9 6 19 #define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 7 20 #define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 8 21 #define GCC_AGGRE_UFS_PHY_AXI_CLK 9 22 #define GCC_AGGRE_USB3_PRIM_AXI_CLK 10 23 #define GCC_CAMERA_AHB_CLK 11 24 #define GCC_CAMERA_HF_AXI_CLK 12 25 #define GCC_CAMERA_SF_AXI_CLK 13 26 #define GCC_CAMERA_XO_CLK 14 27 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 15 28 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 16 29 #define GCC_CPUSS_AHB_CLK 17 30 #define GCC_CPUSS_AHB_CLK_SRC 18 31 #define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 19 32 #define GCC_DDRSS_GPU_AXI_CLK 20 33 #define GCC_DDRSS_PCIE_SF_CLK 21 34 #define GCC_DISP_AHB_CLK 22 35 #define GCC_DISP_GPLL0_CLK_SRC 23 36 #define GCC_DISP_HF_AXI_CLK 24 37 #define GCC_DISP_SF_AXI_CLK 25 38 #define GCC_DISP_XO_CLK 26 39 #define GCC_GP1_CLK 27 40 #define GCC_GP1_CLK_SRC 28 41 #define GCC_GP2_CLK 29 42 #define GCC_GP2_CLK_SRC 30 43 #define GCC_GP3_CLK 31 44 #define GCC_GP3_CLK_SRC 32 45 #define GCC_GPU_CFG_AHB_CLK 33 46 #define GCC_GPU_GPLL0_CLK_SRC 34 47 #define GCC_GPU_GPLL0_DIV_CLK_SRC 35 48 #define GCC_GPU_IREF_EN 36 49 #define GCC_GPU_MEMNOC_GFX_CLK 37 50 #define GCC_GPU_SNOC_DVM_GFX_CLK 38 51 #define GCC_PCIE0_PHY_RCHNG_CLK 39 52 #define GCC_PCIE1_PHY_RCHNG_CLK 40 53 #define GCC_PCIE_0_AUX_CLK 41 54 #define GCC_PCIE_0_AUX_CLK_SRC 42 55 #define GCC_PCIE_0_CFG_AHB_CLK 43 56 #define GCC_PCIE_0_MSTR_AXI_CLK 44 57 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 45 58 #define GCC_PCIE_0_PIPE_CLK 46 59 #define GCC_PCIE_0_PIPE_CLK_SRC 47 60 #define GCC_PCIE_0_SLV_AXI_CLK 48 61 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49 62 #define GCC_PCIE_1_AUX_CLK 50 63 #define GCC_PCIE_1_AUX_CLK_SRC 51 64 #define GCC_PCIE_1_CFG_AHB_CLK 52 65 #define GCC_PCIE_1_MSTR_AXI_CLK 53 66 #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 54 67 #define GCC_PCIE_1_PIPE_CLK 55 68 #define GCC_PCIE_1_PIPE_CLK_SRC 56 69 #define GCC_PCIE_1_SLV_AXI_CLK 57 70 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 58 71 #define GCC_PCIE_THROTTLE_CORE_CLK 59 72 #define GCC_PDM2_CLK 60 73 #define GCC_PDM2_CLK_SRC 61 74 #define GCC_PDM_AHB_CLK 62 75 #define GCC_PDM_XO4_CLK 63 76 #define GCC_QMIP_CAMERA_NRT_AHB_CLK 64 77 #define GCC_QMIP_CAMERA_RT_AHB_CLK 65 78 #define GCC_QMIP_DISP_AHB_CLK 66 79 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 67 80 #define GCC_QUPV3_WRAP0_CORE_2X_CLK 68 81 #define GCC_QUPV3_WRAP0_CORE_CLK 69 82 #define GCC_QUPV3_WRAP0_S0_CLK 70 83 #define GCC_QUPV3_WRAP0_S0_CLK_SRC 71 84 #define GCC_QUPV3_WRAP0_S1_CLK 72 85 #define GCC_QUPV3_WRAP0_S1_CLK_SRC 73 86 #define GCC_QUPV3_WRAP0_S2_CLK 74 87 #define GCC_QUPV3_WRAP0_S2_CLK_SRC 75 88 #define GCC_QUPV3_WRAP0_S3_CLK 76 89 #define GCC_QUPV3_WRAP0_S3_CLK_SRC 77 90 #define GCC_QUPV3_WRAP0_S4_CLK 78 91 #define GCC_QUPV3_WRAP0_S4_CLK_SRC 79 92 #define GCC_QUPV3_WRAP0_S5_CLK 80 93 #define GCC_QUPV3_WRAP0_S5_CLK_SRC 81 94 #define GCC_QUPV3_WRAP0_S6_CLK 82 95 #define GCC_QUPV3_WRAP0_S6_CLK_SRC 83 96 #define GCC_QUPV3_WRAP0_S7_CLK 84 97 #define GCC_QUPV3_WRAP0_S7_CLK_SRC 85 98 #define GCC_QUPV3_WRAP1_CORE_2X_CLK 86 99 #define GCC_QUPV3_WRAP1_CORE_CLK 87 100 #define GCC_QUPV3_WRAP1_S0_CLK 88 101 #define GCC_QUPV3_WRAP1_S0_CLK_SRC 89 102 #define GCC_QUPV3_WRAP1_S1_CLK 90 103 #define GCC_QUPV3_WRAP1_S1_CLK_SRC 91 104 #define GCC_QUPV3_WRAP1_S2_CLK 92 105 #define GCC_QUPV3_WRAP1_S2_CLK_SRC 93 106 #define GCC_QUPV3_WRAP1_S3_CLK 94 107 #define GCC_QUPV3_WRAP1_S3_CLK_SRC 95 108 #define GCC_QUPV3_WRAP1_S4_CLK 96 109 #define GCC_QUPV3_WRAP1_S4_CLK_SRC 97 110 #define GCC_QUPV3_WRAP1_S5_CLK 98 111 #define GCC_QUPV3_WRAP1_S5_CLK_SRC 99 112 #define GCC_QUPV3_WRAP1_S6_CLK 100 113 #define GCC_QUPV3_WRAP1_S6_CLK_SRC 101 114 #define GCC_QUPV3_WRAP1_S7_CLK 102 115 #define GCC_QUPV3_WRAP1_S7_CLK_SRC 103 116 #define GCC_QUPV3_WRAP_0_M_AHB_CLK 104 117 #define GCC_QUPV3_WRAP_0_S_AHB_CLK 105 118 #define GCC_QUPV3_WRAP_1_M_AHB_CLK 106 119 #define GCC_QUPV3_WRAP_1_S_AHB_CLK 107 120 #define GCC_SDCC1_AHB_CLK 108 121 #define GCC_SDCC1_APPS_CLK 109 122 #define GCC_SDCC1_APPS_CLK_SRC 110 123 #define GCC_SDCC1_ICE_CORE_CLK 111 124 #define GCC_SDCC1_ICE_CORE_CLK_SRC 112 125 #define GCC_SDCC2_AHB_CLK 113 126 #define GCC_SDCC2_APPS_CLK 114 127 #define GCC_SDCC2_APPS_CLK_SRC 115 128 #define GCC_SDCC4_AHB_CLK 116 129 #define GCC_SDCC4_APPS_CLK 117 130 #define GCC_SDCC4_APPS_CLK_SRC 118 131 #define GCC_SYS_NOC_CPUSS_AHB_CLK 119 132 #define GCC_THROTTLE_PCIE_AHB_CLK 120 133 #define GCC_TITAN_NRT_THROTTLE_CORE_CLK 121 134 #define GCC_TITAN_RT_THROTTLE_CORE_CLK 122 135 #define GCC_UFS_1_CLKREF_EN 123 136 #define GCC_UFS_PHY_AHB_CLK 124 137 #define GCC_UFS_PHY_AXI_CLK 125 138 #define GCC_UFS_PHY_AXI_CLK_SRC 126 139 #define GCC_UFS_PHY_ICE_CORE_CLK 127 140 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 128 141 #define GCC_UFS_PHY_PHY_AUX_CLK 129 142 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 130 143 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 131 144 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 132 145 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 133 146 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 134 147 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 135 148 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 136 149 #define GCC_UFS_PHY_UNIPRO_CORE_CLK 137 150 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 138 151 #define GCC_USB30_PRIM_MASTER_CLK 139 152 #define GCC_USB30_PRIM_MASTER_CLK_SRC 140 153 #define GCC_USB30_PRIM_MOCK_UTMI_CLK 141 154 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 142 155 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 143 156 #define GCC_USB30_PRIM_SLEEP_CLK 144 157 #define GCC_USB30_SEC_MASTER_CLK 145 158 #define GCC_USB30_SEC_MASTER_CLK_SRC 146 159 #define GCC_USB30_SEC_MOCK_UTMI_CLK 147 160 #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 148 161 #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 149 162 #define GCC_USB30_SEC_SLEEP_CLK 150 163 #define GCC_USB3_PRIM_PHY_AUX_CLK 151 164 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 152 165 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 153 166 #define GCC_USB3_PRIM_PHY_PIPE_CLK 154 167 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 155 168 #define GCC_USB3_SEC_PHY_AUX_CLK 156 169 #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 157 170 #define GCC_USB3_SEC_PHY_COM_AUX_CLK 158 171 #define GCC_USB3_SEC_PHY_PIPE_CLK 159 172 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 160 173 #define GCC_VIDEO_AHB_CLK 161 174 #define GCC_VIDEO_AXI0_CLK 162 175 #define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 163 176 #define GCC_VIDEO_XO_CLK 164 177 #define GCC_GPLL0_MAIN_DIV_CDIV 165 178 #define GCC_QSPI_CNOC_PERIPH_AHB_CLK 166 179 #define GCC_QSPI_CORE_CLK 167 180 #define GCC_QSPI_CORE_CLK_SRC 168 181 #define GCC_CFG_NOC_LPASS_CLK 169 182 #define GCC_MSS_GPLL0_MAIN_DIV_CLK_SRC 170 183 #define GCC_MSS_CFG_AHB_CLK 171 184 #define GCC_MSS_OFFLINE_AXI_CLK 172 185 #define GCC_MSS_SNOC_AXI_CLK 173 186 #define GCC_MSS_Q6_MEMNOC_AXI_CLK 174 187 #define GCC_MSS_Q6SS_BOOT_CLK_SRC 175 188 #define GCC_AGGRE_USB3_SEC_AXI_CLK 176 189 #define GCC_AGGRE_NOC_PCIE_TBU_CLK 177 190 #define GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK 178 191 #define GCC_PCIE_CLKREF_EN 179 192 #define GCC_WPSS_AHB_CLK 180 193 #define GCC_WPSS_AHB_BDG_MST_CLK 181 194 #define GCC_WPSS_RSCP_CLK 182 195 #define GCC_EDP_CLKREF_EN 183 196 #define GCC_SEC_CTRL_CLK_SRC 184 197 198 /* GCC power domains */ 199 #define GCC_PCIE_0_GDSC 0 200 #define GCC_PCIE_1_GDSC 1 201 #define GCC_UFS_PHY_GDSC 2 202 #define GCC_USB30_PRIM_GDSC 3 203 #define GCC_USB30_SEC_GDSC 4 204 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 5 205 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 6 206 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 7 207 #define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 8 208 #define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 9 209 210 /* GCC resets */ 211 #define GCC_PCIE_0_BCR 0 212 #define GCC_PCIE_0_PHY_BCR 1 213 #define GCC_PCIE_1_BCR 2 214 #define GCC_PCIE_1_PHY_BCR 3 215 #define GCC_QUSB2PHY_PRIM_BCR 4 216 #define GCC_QUSB2PHY_SEC_BCR 5 217 #define GCC_SDCC1_BCR 6 218 #define GCC_SDCC2_BCR 7 219 #define GCC_SDCC4_BCR 8 220 #define GCC_UFS_PHY_BCR 9 221 #define GCC_USB30_PRIM_BCR 10 222 #define GCC_USB30_SEC_BCR 11 223 #define GCC_USB3_DP_PHY_PRIM_BCR 12 224 #define GCC_USB3_PHY_PRIM_BCR 13 225 #define GCC_USB3PHY_PHY_PRIM_BCR 14 226 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 15 227 228 #endif 229
Indexes created Mon Sep 29 03:10:08 GMT 2025