1 /* $NetBSD: qcom,mmcc-apq8084.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2014, The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_APQ_MMCC_8084_H 9 #define _DT_BINDINGS_CLK_APQ_MMCC_8084_H 10 11 #define MMSS_AHB_CLK_SRC 0 12 #define MMSS_AXI_CLK_SRC 1 13 #define MMPLL0 2 14 #define MMPLL0_VOTE 3 15 #define MMPLL1 4 16 #define MMPLL1_VOTE 5 17 #define MMPLL2 6 18 #define MMPLL3 7 19 #define MMPLL4 8 20 #define CSI0_CLK_SRC 9 21 #define CSI1_CLK_SRC 10 22 #define CSI2_CLK_SRC 11 23 #define CSI3_CLK_SRC 12 24 #define VCODEC0_CLK_SRC 13 25 #define VFE0_CLK_SRC 14 26 #define VFE1_CLK_SRC 15 27 #define MDP_CLK_SRC 16 28 #define PCLK0_CLK_SRC 17 29 #define PCLK1_CLK_SRC 18 30 #define OCMEMNOC_CLK_SRC 19 31 #define GFX3D_CLK_SRC 20 32 #define JPEG0_CLK_SRC 21 33 #define JPEG1_CLK_SRC 22 34 #define JPEG2_CLK_SRC 23 35 #define EDPPIXEL_CLK_SRC 24 36 #define EXTPCLK_CLK_SRC 25 37 #define VP_CLK_SRC 26 38 #define CCI_CLK_SRC 27 39 #define CAMSS_GP0_CLK_SRC 28 40 #define CAMSS_GP1_CLK_SRC 29 41 #define MCLK0_CLK_SRC 30 42 #define MCLK1_CLK_SRC 31 43 #define MCLK2_CLK_SRC 32 44 #define MCLK3_CLK_SRC 33 45 #define CSI0PHYTIMER_CLK_SRC 34 46 #define CSI1PHYTIMER_CLK_SRC 35 47 #define CSI2PHYTIMER_CLK_SRC 36 48 #define CPP_CLK_SRC 37 49 #define BYTE0_CLK_SRC 38 50 #define BYTE1_CLK_SRC 39 51 #define EDPAUX_CLK_SRC 40 52 #define EDPLINK_CLK_SRC 41 53 #define ESC0_CLK_SRC 42 54 #define ESC1_CLK_SRC 43 55 #define HDMI_CLK_SRC 44 56 #define VSYNC_CLK_SRC 45 57 #define MMSS_RBCPR_CLK_SRC 46 58 #define RBBMTIMER_CLK_SRC 47 59 #define MAPLE_CLK_SRC 48 60 #define VDP_CLK_SRC 49 61 #define VPU_BUS_CLK_SRC 50 62 #define MMSS_CXO_CLK 51 63 #define MMSS_SLEEPCLK_CLK 52 64 #define AVSYNC_AHB_CLK 53 65 #define AVSYNC_EDPPIXEL_CLK 54 66 #define AVSYNC_EXTPCLK_CLK 55 67 #define AVSYNC_PCLK0_CLK 56 68 #define AVSYNC_PCLK1_CLK 57 69 #define AVSYNC_VP_CLK 58 70 #define CAMSS_AHB_CLK 59 71 #define CAMSS_CCI_CCI_AHB_CLK 60 72 #define CAMSS_CCI_CCI_CLK 61 73 #define CAMSS_CSI0_AHB_CLK 62 74 #define CAMSS_CSI0_CLK 63 75 #define CAMSS_CSI0PHY_CLK 64 76 #define CAMSS_CSI0PIX_CLK 65 77 #define CAMSS_CSI0RDI_CLK 66 78 #define CAMSS_CSI1_AHB_CLK 67 79 #define CAMSS_CSI1_CLK 68 80 #define CAMSS_CSI1PHY_CLK 69 81 #define CAMSS_CSI1PIX_CLK 70 82 #define CAMSS_CSI1RDI_CLK 71 83 #define CAMSS_CSI2_AHB_CLK 72 84 #define CAMSS_CSI2_CLK 73 85 #define CAMSS_CSI2PHY_CLK 74 86 #define CAMSS_CSI2PIX_CLK 75 87 #define CAMSS_CSI2RDI_CLK 76 88 #define CAMSS_CSI3_AHB_CLK 77 89 #define CAMSS_CSI3_CLK 78 90 #define CAMSS_CSI3PHY_CLK 79 91 #define CAMSS_CSI3PIX_CLK 80 92 #define CAMSS_CSI3RDI_CLK 81 93 #define CAMSS_CSI_VFE0_CLK 82 94 #define CAMSS_CSI_VFE1_CLK 83 95 #define CAMSS_GP0_CLK 84 96 #define CAMSS_GP1_CLK 85 97 #define CAMSS_ISPIF_AHB_CLK 86 98 #define CAMSS_JPEG_JPEG0_CLK 87 99 #define CAMSS_JPEG_JPEG1_CLK 88 100 #define CAMSS_JPEG_JPEG2_CLK 89 101 #define CAMSS_JPEG_JPEG_AHB_CLK 90 102 #define CAMSS_JPEG_JPEG_AXI_CLK 91 103 #define CAMSS_MCLK0_CLK 92 104 #define CAMSS_MCLK1_CLK 93 105 #define CAMSS_MCLK2_CLK 94 106 #define CAMSS_MCLK3_CLK 95 107 #define CAMSS_MICRO_AHB_CLK 96 108 #define CAMSS_PHY0_CSI0PHYTIMER_CLK 97 109 #define CAMSS_PHY1_CSI1PHYTIMER_CLK 98 110 #define CAMSS_PHY2_CSI2PHYTIMER_CLK 99 111 #define CAMSS_TOP_AHB_CLK 100 112 #define CAMSS_VFE_CPP_AHB_CLK 101 113 #define CAMSS_VFE_CPP_CLK 102 114 #define CAMSS_VFE_VFE0_CLK 103 115 #define CAMSS_VFE_VFE1_CLK 104 116 #define CAMSS_VFE_VFE_AHB_CLK 105 117 #define CAMSS_VFE_VFE_AXI_CLK 106 118 #define MDSS_AHB_CLK 107 119 #define MDSS_AXI_CLK 108 120 #define MDSS_BYTE0_CLK 109 121 #define MDSS_BYTE1_CLK 110 122 #define MDSS_EDPAUX_CLK 111 123 #define MDSS_EDPLINK_CLK 112 124 #define MDSS_EDPPIXEL_CLK 113 125 #define MDSS_ESC0_CLK 114 126 #define MDSS_ESC1_CLK 115 127 #define MDSS_EXTPCLK_CLK 116 128 #define MDSS_HDMI_AHB_CLK 117 129 #define MDSS_HDMI_CLK 118 130 #define MDSS_MDP_CLK 119 131 #define MDSS_MDP_LUT_CLK 120 132 #define MDSS_PCLK0_CLK 121 133 #define MDSS_PCLK1_CLK 122 134 #define MDSS_VSYNC_CLK 123 135 #define MMSS_RBCPR_AHB_CLK 124 136 #define MMSS_RBCPR_CLK 125 137 #define MMSS_SPDM_AHB_CLK 126 138 #define MMSS_SPDM_AXI_CLK 127 139 #define MMSS_SPDM_CSI0_CLK 128 140 #define MMSS_SPDM_GFX3D_CLK 129 141 #define MMSS_SPDM_JPEG0_CLK 130 142 #define MMSS_SPDM_JPEG1_CLK 131 143 #define MMSS_SPDM_JPEG2_CLK 132 144 #define MMSS_SPDM_MDP_CLK 133 145 #define MMSS_SPDM_PCLK0_CLK 134 146 #define MMSS_SPDM_PCLK1_CLK 135 147 #define MMSS_SPDM_VCODEC0_CLK 136 148 #define MMSS_SPDM_VFE0_CLK 137 149 #define MMSS_SPDM_VFE1_CLK 138 150 #define MMSS_SPDM_RM_AXI_CLK 139 151 #define MMSS_SPDM_RM_OCMEMNOC_CLK 140 152 #define MMSS_MISC_AHB_CLK 141 153 #define MMSS_MMSSNOC_AHB_CLK 142 154 #define MMSS_MMSSNOC_BTO_AHB_CLK 143 155 #define MMSS_MMSSNOC_AXI_CLK 144 156 #define MMSS_S0_AXI_CLK 145 157 #define OCMEMCX_AHB_CLK 146 158 #define OCMEMCX_OCMEMNOC_CLK 147 159 #define OXILI_OCMEMGX_CLK 148 160 #define OXILI_GFX3D_CLK 149 161 #define OXILI_RBBMTIMER_CLK 150 162 #define OXILICX_AHB_CLK 151 163 #define VENUS0_AHB_CLK 152 164 #define VENUS0_AXI_CLK 153 165 #define VENUS0_CORE0_VCODEC_CLK 154 166 #define VENUS0_CORE1_VCODEC_CLK 155 167 #define VENUS0_OCMEMNOC_CLK 156 168 #define VENUS0_VCODEC0_CLK 157 169 #define VPU_AHB_CLK 158 170 #define VPU_AXI_CLK 159 171 #define VPU_BUS_CLK 160 172 #define VPU_CXO_CLK 161 173 #define VPU_MAPLE_CLK 162 174 #define VPU_SLEEP_CLK 163 175 #define VPU_VDP_CLK 164 176 177 /* GDSCs */ 178 #define VENUS0_GDSC 0 179 #define VENUS0_CORE0_GDSC 1 180 #define VENUS0_CORE1_GDSC 2 181 #define MDSS_GDSC 3 182 #define CAMSS_JPEG_GDSC 4 183 #define CAMSS_VFE_GDSC 5 184 #define OXILI_GDSC 6 185 #define OXILICX_GDSC 7 186 187 #endif 188
Indexes created Tue Sep 30 20:09:53 GMT 2025