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      1 /*	$NetBSD: qcom,mmcc-msm8994.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only */
      4 /*
      5  * Copyright (c) 2020, Konrad Dybcio
      6  */
      7 
      8 #ifndef _DT_BINDINGS_CLK_MSM_MMCC_8994_H
      9 #define _DT_BINDINGS_CLK_MSM_MMCC_8994_H
     10 
     11 /* Clocks */
     12 #define MMPLL0_EARLY					0
     13 #define MMPLL0_PLL						1
     14 #define MMPLL1_EARLY					2
     15 #define MMPLL1_PLL						3
     16 #define MMPLL3_EARLY					4
     17 #define MMPLL3_PLL						5
     18 #define MMPLL4_EARLY					6
     19 #define MMPLL4_PLL						7
     20 #define MMPLL5_EARLY					8
     21 #define MMPLL5_PLL						9
     22 #define AXI_CLK_SRC						10
     23 #define RBBMTIMER_CLK_SRC				11
     24 #define PCLK0_CLK_SRC					12
     25 #define PCLK1_CLK_SRC					13
     26 #define MDP_CLK_SRC						14
     27 #define VSYNC_CLK_SRC					15
     28 #define BYTE0_CLK_SRC					16
     29 #define BYTE1_CLK_SRC					17
     30 #define ESC0_CLK_SRC					18
     31 #define ESC1_CLK_SRC					19
     32 #define MDSS_AHB_CLK					20
     33 #define MDSS_PCLK0_CLK					21
     34 #define MDSS_PCLK1_CLK					22
     35 #define MDSS_VSYNC_CLK					23
     36 #define MDSS_BYTE0_CLK					24
     37 #define MDSS_BYTE1_CLK					25
     38 #define MDSS_ESC0_CLK					26
     39 #define MDSS_ESC1_CLK					27
     40 #define CSI0_CLK_SRC					28
     41 #define CSI1_CLK_SRC					29
     42 #define CSI2_CLK_SRC					30
     43 #define CSI3_CLK_SRC					31
     44 #define VFE0_CLK_SRC					32
     45 #define VFE1_CLK_SRC					33
     46 #define CPP_CLK_SRC						34
     47 #define JPEG0_CLK_SRC					35
     48 #define JPEG1_CLK_SRC					36
     49 #define JPEG2_CLK_SRC					37
     50 #define CSI2PHYTIMER_CLK_SRC			38
     51 #define FD_CORE_CLK_SRC					39
     52 #define OCMEMNOC_CLK_SRC				40
     53 #define CCI_CLK_SRC						41
     54 #define MMSS_GP0_CLK_SRC				42
     55 #define MMSS_GP1_CLK_SRC				43
     56 #define JPEG_DMA_CLK_SRC				44
     57 #define MCLK0_CLK_SRC					45
     58 #define MCLK1_CLK_SRC					46
     59 #define MCLK2_CLK_SRC					47
     60 #define MCLK3_CLK_SRC					48
     61 #define CSI0PHYTIMER_CLK_SRC			49
     62 #define CSI1PHYTIMER_CLK_SRC			50
     63 #define EXTPCLK_CLK_SRC					51
     64 #define HDMI_CLK_SRC					52
     65 #define CAMSS_AHB_CLK					53
     66 #define CAMSS_CCI_CCI_AHB_CLK			54
     67 #define CAMSS_CCI_CCI_CLK				55
     68 #define CAMSS_VFE_CPP_AHB_CLK			56
     69 #define CAMSS_VFE_CPP_AXI_CLK			57
     70 #define CAMSS_VFE_CPP_CLK				58
     71 #define CAMSS_CSI0_AHB_CLK				59
     72 #define CAMSS_CSI0_CLK					60
     73 #define CAMSS_CSI0PHY_CLK				61
     74 #define CAMSS_CSI0PIX_CLK				62
     75 #define CAMSS_CSI0RDI_CLK				63
     76 #define CAMSS_CSI1_AHB_CLK				64
     77 #define CAMSS_CSI1_CLK					65
     78 #define CAMSS_CSI1PHY_CLK				66
     79 #define CAMSS_CSI1PIX_CLK				67
     80 #define CAMSS_CSI1RDI_CLK				68
     81 #define CAMSS_CSI2_AHB_CLK				69
     82 #define CAMSS_CSI2_CLK					70
     83 #define CAMSS_CSI2PHY_CLK				71
     84 #define CAMSS_CSI2PIX_CLK				72
     85 #define CAMSS_CSI2RDI_CLK				73
     86 #define CAMSS_CSI3_AHB_CLK				74
     87 #define CAMSS_CSI3_CLK					75
     88 #define CAMSS_CSI3PHY_CLK				76
     89 #define CAMSS_CSI3PIX_CLK				77
     90 #define CAMSS_CSI3RDI_CLK				78
     91 #define CAMSS_CSI_VFE0_CLK				79
     92 #define CAMSS_CSI_VFE1_CLK				80
     93 #define CAMSS_GP0_CLK					81
     94 #define CAMSS_GP1_CLK					82
     95 #define CAMSS_ISPIF_AHB_CLK				83
     96 #define CAMSS_JPEG_DMA_CLK				84
     97 #define CAMSS_JPEG_JPEG0_CLK			85
     98 #define CAMSS_JPEG_JPEG1_CLK			86
     99 #define CAMSS_JPEG_JPEG2_CLK			87
    100 #define CAMSS_JPEG_JPEG_AHB_CLK			88
    101 #define CAMSS_JPEG_JPEG_AXI_CLK			89
    102 #define CAMSS_MCLK0_CLK					90
    103 #define CAMSS_MCLK1_CLK					91
    104 #define CAMSS_MCLK2_CLK					92
    105 #define CAMSS_MCLK3_CLK					93
    106 #define CAMSS_MICRO_AHB_CLK				94
    107 #define CAMSS_PHY0_CSI0PHYTIMER_CLK		95
    108 #define CAMSS_PHY1_CSI1PHYTIMER_CLK		96
    109 #define CAMSS_PHY2_CSI2PHYTIMER_CLK		97
    110 #define CAMSS_TOP_AHB_CLK				98
    111 #define CAMSS_VFE_VFE0_CLK				99
    112 #define CAMSS_VFE_VFE1_CLK				100
    113 #define CAMSS_VFE_VFE_AHB_CLK			101
    114 #define CAMSS_VFE_VFE_AXI_CLK			102
    115 #define FD_AXI_CLK						103
    116 #define FD_CORE_CLK						104
    117 #define FD_CORE_UAR_CLK					105
    118 #define MDSS_AXI_CLK					106
    119 #define MDSS_EXTPCLK_CLK				107
    120 #define MDSS_HDMI_AHB_CLK				108
    121 #define MDSS_HDMI_CLK					109
    122 #define MDSS_MDP_CLK					110
    123 #define MMSS_MISC_AHB_CLK				111
    124 #define MMSS_MMSSNOC_AXI_CLK			112
    125 #define MMSS_S0_AXI_CLK					113
    126 #define OCMEMCX_OCMEMNOC_CLK			114
    127 #define OXILI_GFX3D_CLK					115
    128 #define OXILI_RBBMTIMER_CLK				116
    129 #define OXILICX_AHB_CLK					117
    130 #define VENUS0_AHB_CLK					118
    131 #define VENUS0_AXI_CLK					119
    132 #define VENUS0_OCMEMNOC_CLK				120
    133 #define VENUS0_VCODEC0_CLK				121
    134 #define VENUS0_CORE0_VCODEC_CLK			122
    135 #define VENUS0_CORE1_VCODEC_CLK			123
    136 #define VENUS0_CORE2_VCODEC_CLK			124
    137 #define AHB_CLK_SRC						125
    138 #define FD_AHB_CLK						126
    139 
    140 /* GDSCs */
    141 #define VENUS_GDSC						0
    142 #define VENUS_CORE0_GDSC				1
    143 #define VENUS_CORE1_GDSC				2
    144 #define VENUS_CORE2_GDSC				3
    145 #define CAMSS_TOP_GDSC					4
    146 #define MDSS_GDSC						5
    147 #define JPEG_GDSC						6
    148 #define VFE_GDSC						7
    149 #define CPP_GDSC						8
    150 #define OXILI_GX_GDSC					9
    151 #define OXILI_CX_GDSC					10
    152 #define FD_GDSC							11
    153 
    154 /* Resets */
    155 #define CAMSS_MICRO_BCR					0
    156 
    157 #endif
    158