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      1 /*	$NetBSD: qcom,qca8k-nsscc.h,v 1.1.1.1 2026/01/18 05:21:36 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      4 /*
      5  * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
      6  */
      7 
      8 #ifndef _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
      9 #define _DT_BINDINGS_CLK_QCOM_QCA8K_NSS_CC_H
     10 
     11 #define NSS_CC_SWITCH_CORE_CLK_SRC				0
     12 #define NSS_CC_SWITCH_CORE_CLK					1
     13 #define NSS_CC_APB_BRIDGE_CLK					2
     14 #define NSS_CC_MAC0_TX_CLK_SRC					3
     15 #define NSS_CC_MAC0_TX_DIV_CLK_SRC				4
     16 #define NSS_CC_MAC0_TX_CLK					5
     17 #define NSS_CC_MAC0_TX_SRDS1_CLK				6
     18 #define NSS_CC_MAC0_RX_CLK_SRC					7
     19 #define NSS_CC_MAC0_RX_DIV_CLK_SRC				8
     20 #define NSS_CC_MAC0_RX_CLK					9
     21 #define NSS_CC_MAC0_RX_SRDS1_CLK				10
     22 #define NSS_CC_MAC1_TX_CLK_SRC					11
     23 #define NSS_CC_MAC1_TX_DIV_CLK_SRC				12
     24 #define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_DIV_CLK_SRC		13
     25 #define NSS_CC_MAC1_SRDS1_CH0_RX_CLK				14
     26 #define NSS_CC_MAC1_TX_CLK					15
     27 #define NSS_CC_MAC1_GEPHY0_TX_CLK				16
     28 #define NSS_CC_MAC1_SRDS1_CH0_XGMII_RX_CLK			17
     29 #define NSS_CC_MAC1_RX_CLK_SRC					18
     30 #define NSS_CC_MAC1_RX_DIV_CLK_SRC				19
     31 #define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_DIV_CLK_SRC		20
     32 #define NSS_CC_MAC1_SRDS1_CH0_TX_CLK				21
     33 #define NSS_CC_MAC1_RX_CLK					22
     34 #define NSS_CC_MAC1_GEPHY0_RX_CLK				23
     35 #define NSS_CC_MAC1_SRDS1_CH0_XGMII_TX_CLK			24
     36 #define NSS_CC_MAC2_TX_CLK_SRC					25
     37 #define NSS_CC_MAC2_TX_DIV_CLK_SRC				26
     38 #define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_DIV_CLK_SRC		27
     39 #define NSS_CC_MAC2_SRDS1_CH1_RX_CLK				28
     40 #define NSS_CC_MAC2_TX_CLK					29
     41 #define NSS_CC_MAC2_GEPHY1_TX_CLK				30
     42 #define NSS_CC_MAC2_SRDS1_CH1_XGMII_RX_CLK			31
     43 #define NSS_CC_MAC2_RX_CLK_SRC					32
     44 #define NSS_CC_MAC2_RX_DIV_CLK_SRC				33
     45 #define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_DIV_CLK_SRC		34
     46 #define NSS_CC_MAC2_SRDS1_CH1_TX_CLK				35
     47 #define NSS_CC_MAC2_RX_CLK					36
     48 #define NSS_CC_MAC2_GEPHY1_RX_CLK				37
     49 #define NSS_CC_MAC2_SRDS1_CH1_XGMII_TX_CLK			38
     50 #define NSS_CC_MAC3_TX_CLK_SRC					39
     51 #define NSS_CC_MAC3_TX_DIV_CLK_SRC				40
     52 #define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_DIV_CLK_SRC		41
     53 #define NSS_CC_MAC3_SRDS1_CH2_RX_CLK				42
     54 #define NSS_CC_MAC3_TX_CLK					43
     55 #define NSS_CC_MAC3_GEPHY2_TX_CLK				44
     56 #define NSS_CC_MAC3_SRDS1_CH2_XGMII_RX_CLK			45
     57 #define NSS_CC_MAC3_RX_CLK_SRC					46
     58 #define NSS_CC_MAC3_RX_DIV_CLK_SRC				47
     59 #define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_DIV_CLK_SRC		48
     60 #define NSS_CC_MAC3_SRDS1_CH2_TX_CLK				49
     61 #define NSS_CC_MAC3_RX_CLK					50
     62 #define NSS_CC_MAC3_GEPHY2_RX_CLK				51
     63 #define NSS_CC_MAC3_SRDS1_CH2_XGMII_TX_CLK			52
     64 #define NSS_CC_MAC4_TX_CLK_SRC					53
     65 #define NSS_CC_MAC4_TX_DIV_CLK_SRC				54
     66 #define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_DIV_CLK_SRC		55
     67 #define NSS_CC_MAC4_SRDS1_CH3_RX_CLK				56
     68 #define NSS_CC_MAC4_TX_CLK					57
     69 #define NSS_CC_MAC4_GEPHY3_TX_CLK				58
     70 #define NSS_CC_MAC4_SRDS1_CH3_XGMII_RX_CLK			59
     71 #define NSS_CC_MAC4_RX_CLK_SRC					60
     72 #define NSS_CC_MAC4_RX_DIV_CLK_SRC				61
     73 #define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_DIV_CLK_SRC		62
     74 #define NSS_CC_MAC4_SRDS1_CH3_TX_CLK				63
     75 #define NSS_CC_MAC4_RX_CLK					64
     76 #define NSS_CC_MAC4_GEPHY3_RX_CLK				65
     77 #define NSS_CC_MAC4_SRDS1_CH3_XGMII_TX_CLK			66
     78 #define NSS_CC_MAC5_TX_CLK_SRC					67
     79 #define NSS_CC_MAC5_TX_DIV_CLK_SRC				68
     80 #define NSS_CC_MAC5_TX_SRDS0_CLK				69
     81 #define NSS_CC_MAC5_TX_CLK					70
     82 #define NSS_CC_MAC5_RX_CLK_SRC					71
     83 #define NSS_CC_MAC5_RX_DIV_CLK_SRC				72
     84 #define NSS_CC_MAC5_RX_SRDS0_CLK				73
     85 #define NSS_CC_MAC5_RX_CLK					74
     86 #define NSS_CC_MAC5_TX_SRDS0_CLK_SRC				75
     87 #define NSS_CC_MAC5_RX_SRDS0_CLK_SRC				76
     88 #define NSS_CC_AHB_CLK_SRC					77
     89 #define NSS_CC_AHB_CLK						78
     90 #define NSS_CC_SEC_CTRL_AHB_CLK					79
     91 #define NSS_CC_TLMM_CLK						80
     92 #define NSS_CC_TLMM_AHB_CLK					81
     93 #define NSS_CC_CNOC_AHB_CLK					82
     94 #define NSS_CC_MDIO_AHB_CLK					83
     95 #define NSS_CC_MDIO_MASTER_AHB_CLK				84
     96 #define NSS_CC_SYS_CLK_SRC					85
     97 #define NSS_CC_SRDS0_SYS_CLK					86
     98 #define NSS_CC_SRDS1_SYS_CLK					87
     99 #define NSS_CC_GEPHY0_SYS_CLK					88
    100 #define NSS_CC_GEPHY1_SYS_CLK					89
    101 #define NSS_CC_GEPHY2_SYS_CLK					90
    102 #define NSS_CC_GEPHY3_SYS_CLK					91
    103 #endif
    104