1 /* $NetBSD: qcom,sc8280xp-camcc.h,v 1.1.1.1 2026/01/18 05:21:36 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4 /* 5 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2023, Linaro Ltd. 7 */ 8 9 #ifndef __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__ 10 #define __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__ 11 12 /* CAMCC clocks */ 13 #define CAMCC_PLL0 0 14 #define CAMCC_PLL0_OUT_EVEN 1 15 #define CAMCC_PLL0_OUT_ODD 2 16 #define CAMCC_PLL1 3 17 #define CAMCC_PLL1_OUT_EVEN 4 18 #define CAMCC_PLL2 5 19 #define CAMCC_PLL3 6 20 #define CAMCC_PLL3_OUT_EVEN 7 21 #define CAMCC_PLL4 8 22 #define CAMCC_PLL4_OUT_EVEN 9 23 #define CAMCC_PLL5 10 24 #define CAMCC_PLL5_OUT_EVEN 11 25 #define CAMCC_PLL6 12 26 #define CAMCC_PLL6_OUT_EVEN 13 27 #define CAMCC_PLL7 14 28 #define CAMCC_PLL7_OUT_EVEN 15 29 #define CAMCC_PLL7_OUT_ODD 16 30 #define CAMCC_BPS_AHB_CLK 17 31 #define CAMCC_BPS_AREG_CLK 18 32 #define CAMCC_BPS_AXI_CLK 19 33 #define CAMCC_BPS_CLK 20 34 #define CAMCC_BPS_CLK_SRC 21 35 #define CAMCC_CAMNOC_AXI_CLK 22 36 #define CAMCC_CAMNOC_AXI_CLK_SRC 23 37 #define CAMCC_CAMNOC_DCD_XO_CLK 24 38 #define CAMCC_CCI_0_CLK 25 39 #define CAMCC_CCI_0_CLK_SRC 26 40 #define CAMCC_CCI_1_CLK 27 41 #define CAMCC_CCI_1_CLK_SRC 28 42 #define CAMCC_CCI_2_CLK 29 43 #define CAMCC_CCI_2_CLK_SRC 30 44 #define CAMCC_CCI_3_CLK 31 45 #define CAMCC_CCI_3_CLK_SRC 32 46 #define CAMCC_CORE_AHB_CLK 33 47 #define CAMCC_CPAS_AHB_CLK 34 48 #define CAMCC_CPHY_RX_CLK_SRC 35 49 #define CAMCC_CSI0PHYTIMER_CLK 36 50 #define CAMCC_CSI0PHYTIMER_CLK_SRC 37 51 #define CAMCC_CSI1PHYTIMER_CLK 38 52 #define CAMCC_CSI1PHYTIMER_CLK_SRC 39 53 #define CAMCC_CSI2PHYTIMER_CLK 40 54 #define CAMCC_CSI2PHYTIMER_CLK_SRC 41 55 #define CAMCC_CSI3PHYTIMER_CLK 42 56 #define CAMCC_CSI3PHYTIMER_CLK_SRC 43 57 #define CAMCC_CSIPHY0_CLK 44 58 #define CAMCC_CSIPHY1_CLK 45 59 #define CAMCC_CSIPHY2_CLK 46 60 #define CAMCC_CSIPHY3_CLK 47 61 #define CAMCC_FAST_AHB_CLK_SRC 48 62 #define CAMCC_GDSC_CLK 49 63 #define CAMCC_ICP_AHB_CLK 50 64 #define CAMCC_ICP_CLK 51 65 #define CAMCC_ICP_CLK_SRC 52 66 #define CAMCC_IFE_0_AXI_CLK 53 67 #define CAMCC_IFE_0_CLK 54 68 #define CAMCC_IFE_0_CLK_SRC 55 69 #define CAMCC_IFE_0_CPHY_RX_CLK 56 70 #define CAMCC_IFE_0_CSID_CLK 57 71 #define CAMCC_IFE_0_CSID_CLK_SRC 58 72 #define CAMCC_IFE_0_DSP_CLK 59 73 #define CAMCC_IFE_1_AXI_CLK 60 74 #define CAMCC_IFE_1_CLK 61 75 #define CAMCC_IFE_1_CLK_SRC 62 76 #define CAMCC_IFE_1_CPHY_RX_CLK 63 77 #define CAMCC_IFE_1_CSID_CLK 64 78 #define CAMCC_IFE_1_CSID_CLK_SRC 65 79 #define CAMCC_IFE_1_DSP_CLK 66 80 #define CAMCC_IFE_2_AXI_CLK 67 81 #define CAMCC_IFE_2_CLK 68 82 #define CAMCC_IFE_2_CLK_SRC 69 83 #define CAMCC_IFE_2_CPHY_RX_CLK 70 84 #define CAMCC_IFE_2_CSID_CLK 71 85 #define CAMCC_IFE_2_CSID_CLK_SRC 72 86 #define CAMCC_IFE_2_DSP_CLK 73 87 #define CAMCC_IFE_3_AXI_CLK 74 88 #define CAMCC_IFE_3_CLK 75 89 #define CAMCC_IFE_3_CLK_SRC 76 90 #define CAMCC_IFE_3_CPHY_RX_CLK 77 91 #define CAMCC_IFE_3_CSID_CLK 78 92 #define CAMCC_IFE_3_CSID_CLK_SRC 79 93 #define CAMCC_IFE_3_DSP_CLK 80 94 #define CAMCC_IFE_LITE_0_CLK 81 95 #define CAMCC_IFE_LITE_0_CLK_SRC 82 96 #define CAMCC_IFE_LITE_0_CPHY_RX_CLK 83 97 #define CAMCC_IFE_LITE_0_CSID_CLK 84 98 #define CAMCC_IFE_LITE_0_CSID_CLK_SRC 85 99 #define CAMCC_IFE_LITE_1_CLK 86 100 #define CAMCC_IFE_LITE_1_CLK_SRC 87 101 #define CAMCC_IFE_LITE_1_CPHY_RX_CLK 88 102 #define CAMCC_IFE_LITE_1_CSID_CLK 89 103 #define CAMCC_IFE_LITE_1_CSID_CLK_SRC 90 104 #define CAMCC_IFE_LITE_2_CLK 91 105 #define CAMCC_IFE_LITE_2_CLK_SRC 92 106 #define CAMCC_IFE_LITE_2_CPHY_RX_CLK 93 107 #define CAMCC_IFE_LITE_2_CSID_CLK 94 108 #define CAMCC_IFE_LITE_2_CSID_CLK_SRC 95 109 #define CAMCC_IFE_LITE_3_CLK 96 110 #define CAMCC_IFE_LITE_3_CLK_SRC 97 111 #define CAMCC_IFE_LITE_3_CPHY_RX_CLK 98 112 #define CAMCC_IFE_LITE_3_CSID_CLK 99 113 #define CAMCC_IFE_LITE_3_CSID_CLK_SRC 100 114 #define CAMCC_IPE_0_AHB_CLK 101 115 #define CAMCC_IPE_0_AREG_CLK 102 116 #define CAMCC_IPE_0_AXI_CLK 103 117 #define CAMCC_IPE_0_CLK 104 118 #define CAMCC_IPE_0_CLK_SRC 105 119 #define CAMCC_IPE_1_AHB_CLK 106 120 #define CAMCC_IPE_1_AREG_CLK 107 121 #define CAMCC_IPE_1_AXI_CLK 108 122 #define CAMCC_IPE_1_CLK 109 123 #define CAMCC_JPEG_CLK 110 124 #define CAMCC_JPEG_CLK_SRC 111 125 #define CAMCC_LRME_CLK 112 126 #define CAMCC_LRME_CLK_SRC 113 127 #define CAMCC_MCLK0_CLK 114 128 #define CAMCC_MCLK0_CLK_SRC 115 129 #define CAMCC_MCLK1_CLK 116 130 #define CAMCC_MCLK1_CLK_SRC 117 131 #define CAMCC_MCLK2_CLK 118 132 #define CAMCC_MCLK2_CLK_SRC 119 133 #define CAMCC_MCLK3_CLK 120 134 #define CAMCC_MCLK3_CLK_SRC 121 135 #define CAMCC_MCLK4_CLK 122 136 #define CAMCC_MCLK4_CLK_SRC 123 137 #define CAMCC_MCLK5_CLK 124 138 #define CAMCC_MCLK5_CLK_SRC 125 139 #define CAMCC_MCLK6_CLK 126 140 #define CAMCC_MCLK6_CLK_SRC 127 141 #define CAMCC_MCLK7_CLK 128 142 #define CAMCC_MCLK7_CLK_SRC 129 143 #define CAMCC_SLEEP_CLK 130 144 #define CAMCC_SLEEP_CLK_SRC 131 145 #define CAMCC_SLOW_AHB_CLK_SRC 132 146 #define CAMCC_XO_CLK_SRC 133 147 148 /* CAMCC resets */ 149 #define CAMCC_BPS_BCR 0 150 #define CAMCC_CAMNOC_BCR 1 151 #define CAMCC_CCI_BCR 2 152 #define CAMCC_CPAS_BCR 3 153 #define CAMCC_CSI0PHY_BCR 4 154 #define CAMCC_CSI1PHY_BCR 5 155 #define CAMCC_CSI2PHY_BCR 6 156 #define CAMCC_CSI3PHY_BCR 7 157 #define CAMCC_ICP_BCR 8 158 #define CAMCC_IFE_0_BCR 9 159 #define CAMCC_IFE_1_BCR 10 160 #define CAMCC_IFE_2_BCR 11 161 #define CAMCC_IFE_3_BCR 12 162 #define CAMCC_IFE_LITE_0_BCR 13 163 #define CAMCC_IFE_LITE_1_BCR 14 164 #define CAMCC_IFE_LITE_2_BCR 15 165 #define CAMCC_IFE_LITE_3_BCR 16 166 #define CAMCC_IPE_0_BCR 17 167 #define CAMCC_IPE_1_BCR 18 168 #define CAMCC_JPEG_BCR 19 169 #define CAMCC_LRME_BCR 20 170 171 /* CAMCC GDSCRs */ 172 #define BPS_GDSC 0 173 #define IFE_0_GDSC 1 174 #define IFE_1_GDSC 2 175 #define IFE_2_GDSC 3 176 #define IFE_3_GDSC 4 177 #define IPE_0_GDSC 5 178 #define IPE_1_GDSC 6 179 #define TITAN_TOP_GDSC 7 180 181 #endif /* __DT_BINDINGS_CLK_QCOM_CAMCC_SC8280XP_H__ */ 182
Indexes created Sat Apr 25 00:22:52 UTC 2026