11.1Sskrll/*	$NetBSD: qcom,sm4450-gpucc.h,v 1.1.1.1 2026/01/18 05:21:36 skrll Exp $	*/
21.1Sskrll
31.1Sskrll/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
41.1Sskrll/*
51.1Sskrll * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
61.1Sskrll */
71.1Sskrll
81.1Sskrll#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
91.1Sskrll#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM4450_H
101.1Sskrll
111.1Sskrll/* GPU_CC clocks */
121.1Sskrll#define GPU_CC_AHB_CLK						0
131.1Sskrll#define GPU_CC_CB_CLK						1
141.1Sskrll#define GPU_CC_CRC_AHB_CLK					2
151.1Sskrll#define GPU_CC_CX_FF_CLK					3
161.1Sskrll#define GPU_CC_CX_GFX3D_CLK					4
171.1Sskrll#define GPU_CC_CX_GFX3D_SLV_CLK					5
181.1Sskrll#define GPU_CC_CX_GMU_CLK					6
191.1Sskrll#define GPU_CC_CX_SNOC_DVM_CLK					7
201.1Sskrll#define GPU_CC_CXO_AON_CLK					8
211.1Sskrll#define GPU_CC_CXO_CLK						9
221.1Sskrll#define GPU_CC_DEMET_CLK					10
231.1Sskrll#define GPU_CC_DEMET_DIV_CLK_SRC				11
241.1Sskrll#define GPU_CC_FF_CLK_SRC					12
251.1Sskrll#define GPU_CC_FREQ_MEASURE_CLK					13
261.1Sskrll#define GPU_CC_GMU_CLK_SRC					14
271.1Sskrll#define GPU_CC_GX_CXO_CLK					15
281.1Sskrll#define GPU_CC_GX_FF_CLK					16
291.1Sskrll#define GPU_CC_GX_GFX3D_CLK					17
301.1Sskrll#define GPU_CC_GX_GFX3D_CLK_SRC					18
311.1Sskrll#define GPU_CC_GX_GFX3D_RDVM_CLK				19
321.1Sskrll#define GPU_CC_GX_GMU_CLK					20
331.1Sskrll#define GPU_CC_GX_VSENSE_CLK					21
341.1Sskrll#define GPU_CC_HUB_AHB_DIV_CLK_SRC				22
351.1Sskrll#define GPU_CC_HUB_AON_CLK					23
361.1Sskrll#define GPU_CC_HUB_CLK_SRC					24
371.1Sskrll#define GPU_CC_HUB_CX_INT_CLK					25
381.1Sskrll#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC				26
391.1Sskrll#define GPU_CC_MEMNOC_GFX_CLK					27
401.1Sskrll#define GPU_CC_MND1X_0_GFX3D_CLK				28
411.1Sskrll#define GPU_CC_PLL0						29
421.1Sskrll#define GPU_CC_PLL1						30
431.1Sskrll#define GPU_CC_SLEEP_CLK					31
441.1Sskrll#define GPU_CC_XO_CLK_SRC					32
451.1Sskrll#define GPU_CC_XO_DIV_CLK_SRC					33
461.1Sskrll
471.1Sskrll/* GPU_CC power domains */
481.1Sskrll#define GPU_CC_CX_GDSC						0
491.1Sskrll#define GPU_CC_GX_GDSC						1
501.1Sskrll
511.1Sskrll/* GPU_CC resets */
521.1Sskrll#define GPU_CC_ACD_BCR						0
531.1Sskrll#define GPU_CC_CB_BCR						1
541.1Sskrll#define GPU_CC_CX_BCR						2
551.1Sskrll#define GPU_CC_FAST_HUB_BCR					3
561.1Sskrll#define GPU_CC_FF_BCR						4
571.1Sskrll#define GPU_CC_GFX3D_AON_BCR					5
581.1Sskrll#define GPU_CC_GMU_BCR						6
591.1Sskrll#define GPU_CC_GX_BCR						7
601.1Sskrll#define GPU_CC_XO_BCR						8
611.1Sskrll#define GPU_CC_GX_ACD_IROOT_BCR					9
621.1Sskrll#define GPU_CC_RBCPR_BCR					10
631.1Sskrll
641.1Sskrll#endif
65