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      1 /*	$NetBSD: qcom,sm6350-camcc.h,v 1.1.1.1 2026/01/18 05:21:37 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      4 /*
      5  * Copyright (c) 2022, The Linux Foundation. All rights reserved.
      6  * Copyright (c) 2022, Linaro Limited
      7  */
      8 
      9 #ifndef _DT_BINDINGS_CLK_QCOM_CAMCC_SM6350_H
     10 #define _DT_BINDINGS_CLK_QCOM_CAMCC_SM6350_H
     11 
     12 /* CAMCC clocks */
     13 #define CAMCC_PLL2_OUT_EARLY		0
     14 #define CAMCC_PLL0			1
     15 #define CAMCC_PLL0_OUT_EVEN		2
     16 #define CAMCC_PLL1			3
     17 #define CAMCC_PLL1_OUT_EVEN		4
     18 #define CAMCC_PLL2			5
     19 #define CAMCC_PLL2_OUT_MAIN		6
     20 #define CAMCC_PLL3			7
     21 #define CAMCC_BPS_AHB_CLK		8
     22 #define CAMCC_BPS_AREG_CLK		9
     23 #define CAMCC_BPS_AXI_CLK		10
     24 #define CAMCC_BPS_CLK			11
     25 #define CAMCC_BPS_CLK_SRC		12
     26 #define CAMCC_CAMNOC_ATB_CLK		13
     27 #define CAMCC_CAMNOC_AXI_CLK		14
     28 #define CAMCC_CCI_0_CLK		15
     29 #define CAMCC_CCI_0_CLK_SRC		16
     30 #define CAMCC_CCI_1_CLK		17
     31 #define CAMCC_CCI_1_CLK_SRC		18
     32 #define CAMCC_CORE_AHB_CLK		19
     33 #define CAMCC_CPAS_AHB_CLK		20
     34 #define CAMCC_CPHY_RX_CLK_SRC		21
     35 #define CAMCC_CSI0PHYTIMER_CLK		22
     36 #define CAMCC_CSI0PHYTIMER_CLK_SRC	23
     37 #define CAMCC_CSI1PHYTIMER_CLK		24
     38 #define CAMCC_CSI1PHYTIMER_CLK_SRC	25
     39 #define CAMCC_CSI2PHYTIMER_CLK		26
     40 #define CAMCC_CSI2PHYTIMER_CLK_SRC	27
     41 #define CAMCC_CSI3PHYTIMER_CLK		28
     42 #define CAMCC_CSI3PHYTIMER_CLK_SRC	29
     43 #define CAMCC_CSIPHY0_CLK		30
     44 #define CAMCC_CSIPHY1_CLK		31
     45 #define CAMCC_CSIPHY2_CLK		32
     46 #define CAMCC_CSIPHY3_CLK		33
     47 #define CAMCC_FAST_AHB_CLK_SRC		34
     48 #define CAMCC_ICP_APB_CLK		35
     49 #define CAMCC_ICP_ATB_CLK		36
     50 #define CAMCC_ICP_CLK			37
     51 #define CAMCC_ICP_CLK_SRC		38
     52 #define CAMCC_ICP_CTI_CLK		39
     53 #define CAMCC_ICP_TS_CLK		40
     54 #define CAMCC_IFE_0_AXI_CLK		41
     55 #define CAMCC_IFE_0_CLK		42
     56 #define CAMCC_IFE_0_CLK_SRC		43
     57 #define CAMCC_IFE_0_CPHY_RX_CLK	44
     58 #define CAMCC_IFE_0_CSID_CLK		45
     59 #define CAMCC_IFE_0_CSID_CLK_SRC	46
     60 #define CAMCC_IFE_0_DSP_CLK		47
     61 #define CAMCC_IFE_1_AXI_CLK		48
     62 #define CAMCC_IFE_1_CLK		49
     63 #define CAMCC_IFE_1_CLK_SRC		50
     64 #define CAMCC_IFE_1_CPHY_RX_CLK	51
     65 #define CAMCC_IFE_1_CSID_CLK		52
     66 #define CAMCC_IFE_1_CSID_CLK_SRC	53
     67 #define CAMCC_IFE_1_DSP_CLK		54
     68 #define CAMCC_IFE_2_AXI_CLK		55
     69 #define CAMCC_IFE_2_CLK		56
     70 #define CAMCC_IFE_2_CLK_SRC		57
     71 #define CAMCC_IFE_2_CPHY_RX_CLK	58
     72 #define CAMCC_IFE_2_CSID_CLK		59
     73 #define CAMCC_IFE_2_CSID_CLK_SRC	60
     74 #define CAMCC_IFE_2_DSP_CLK		61
     75 #define CAMCC_IFE_LITE_CLK		62
     76 #define CAMCC_IFE_LITE_CLK_SRC		63
     77 #define CAMCC_IFE_LITE_CPHY_RX_CLK	64
     78 #define CAMCC_IFE_LITE_CSID_CLK	65
     79 #define CAMCC_IFE_LITE_CSID_CLK_SRC	66
     80 #define CAMCC_IPE_0_AHB_CLK		67
     81 #define CAMCC_IPE_0_AREG_CLK		68
     82 #define CAMCC_IPE_0_AXI_CLK		69
     83 #define CAMCC_IPE_0_CLK		70
     84 #define CAMCC_IPE_0_CLK_SRC		71
     85 #define CAMCC_JPEG_CLK			72
     86 #define CAMCC_JPEG_CLK_SRC		73
     87 #define CAMCC_LRME_CLK			74
     88 #define CAMCC_LRME_CLK_SRC		75
     89 #define CAMCC_MCLK0_CLK		76
     90 #define CAMCC_MCLK0_CLK_SRC		77
     91 #define CAMCC_MCLK1_CLK		78
     92 #define CAMCC_MCLK1_CLK_SRC		79
     93 #define CAMCC_MCLK2_CLK		80
     94 #define CAMCC_MCLK2_CLK_SRC		81
     95 #define CAMCC_MCLK3_CLK		82
     96 #define CAMCC_MCLK3_CLK_SRC		83
     97 #define CAMCC_MCLK4_CLK		84
     98 #define CAMCC_MCLK4_CLK_SRC		85
     99 #define CAMCC_SLOW_AHB_CLK_SRC		86
    100 #define CAMCC_SOC_AHB_CLK		87
    101 #define CAMCC_SYS_TMR_CLK		88
    102 
    103 /* GDSCs */
    104 #define BPS_GDSC			0
    105 #define IPE_0_GDSC			1
    106 #define IFE_0_GDSC			2
    107 #define IFE_1_GDSC			3
    108 #define IFE_2_GDSC			4
    109 #define TITAN_TOP_GDSC			5
    110 
    111 #endif
    112