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      1 /*	$NetBSD: qcom,sm8150-camcc.h,v 1.1.1.1 2026/01/18 05:21:37 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      4 /*
      5  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
      6  */
      7 
      8 #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
      9 #define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM8150_H
     10 
     11 /* CAM_CC clocks */
     12 #define CAM_CC_PLL0					0
     13 #define CAM_CC_PLL0_OUT_EVEN				1
     14 #define CAM_CC_PLL0_OUT_ODD				2
     15 #define CAM_CC_PLL1					3
     16 #define CAM_CC_PLL1_OUT_EVEN				4
     17 #define CAM_CC_PLL2					5
     18 #define CAM_CC_PLL2_OUT_MAIN				6
     19 #define CAM_CC_PLL3					7
     20 #define CAM_CC_PLL3_OUT_EVEN				8
     21 #define CAM_CC_PLL4					9
     22 #define CAM_CC_PLL4_OUT_EVEN				10
     23 #define CAM_CC_BPS_AHB_CLK				11
     24 #define CAM_CC_BPS_AREG_CLK				12
     25 #define CAM_CC_BPS_AXI_CLK				13
     26 #define CAM_CC_BPS_CLK					14
     27 #define CAM_CC_BPS_CLK_SRC				15
     28 #define CAM_CC_CAMNOC_AXI_CLK				16
     29 #define CAM_CC_CAMNOC_AXI_CLK_SRC			17
     30 #define CAM_CC_CAMNOC_DCD_XO_CLK			18
     31 #define CAM_CC_CCI_0_CLK				19
     32 #define CAM_CC_CCI_0_CLK_SRC				20
     33 #define CAM_CC_CCI_1_CLK				21
     34 #define CAM_CC_CCI_1_CLK_SRC				22
     35 #define CAM_CC_CORE_AHB_CLK				23
     36 #define CAM_CC_CPAS_AHB_CLK				24
     37 #define CAM_CC_CPHY_RX_CLK_SRC				25
     38 #define CAM_CC_CSI0PHYTIMER_CLK				26
     39 #define CAM_CC_CSI0PHYTIMER_CLK_SRC			27
     40 #define CAM_CC_CSI1PHYTIMER_CLK				28
     41 #define CAM_CC_CSI1PHYTIMER_CLK_SRC			29
     42 #define CAM_CC_CSI2PHYTIMER_CLK				30
     43 #define CAM_CC_CSI2PHYTIMER_CLK_SRC			31
     44 #define CAM_CC_CSI3PHYTIMER_CLK				32
     45 #define CAM_CC_CSI3PHYTIMER_CLK_SRC			33
     46 #define CAM_CC_CSIPHY0_CLK				34
     47 #define CAM_CC_CSIPHY1_CLK				35
     48 #define CAM_CC_CSIPHY2_CLK				36
     49 #define CAM_CC_CSIPHY3_CLK				37
     50 #define CAM_CC_FAST_AHB_CLK_SRC				38
     51 #define CAM_CC_FD_CORE_CLK				39
     52 #define CAM_CC_FD_CORE_CLK_SRC				40
     53 #define CAM_CC_FD_CORE_UAR_CLK				41
     54 #define CAM_CC_GDSC_CLK					42
     55 #define CAM_CC_ICP_AHB_CLK				43
     56 #define CAM_CC_ICP_CLK					44
     57 #define CAM_CC_ICP_CLK_SRC				45
     58 #define CAM_CC_IFE_0_AXI_CLK				46
     59 #define CAM_CC_IFE_0_CLK				47
     60 #define CAM_CC_IFE_0_CLK_SRC				48
     61 #define CAM_CC_IFE_0_CPHY_RX_CLK			49
     62 #define CAM_CC_IFE_0_CSID_CLK				50
     63 #define CAM_CC_IFE_0_CSID_CLK_SRC			51
     64 #define CAM_CC_IFE_0_DSP_CLK				52
     65 #define CAM_CC_IFE_1_AXI_CLK				53
     66 #define CAM_CC_IFE_1_CLK				54
     67 #define CAM_CC_IFE_1_CLK_SRC				55
     68 #define CAM_CC_IFE_1_CPHY_RX_CLK			56
     69 #define CAM_CC_IFE_1_CSID_CLK				57
     70 #define CAM_CC_IFE_1_CSID_CLK_SRC			58
     71 #define CAM_CC_IFE_1_DSP_CLK				59
     72 #define CAM_CC_IFE_LITE_0_CLK				60
     73 #define CAM_CC_IFE_LITE_0_CLK_SRC			61
     74 #define CAM_CC_IFE_LITE_0_CPHY_RX_CLK			62
     75 #define CAM_CC_IFE_LITE_0_CSID_CLK			63
     76 #define CAM_CC_IFE_LITE_0_CSID_CLK_SRC			64
     77 #define CAM_CC_IFE_LITE_1_CLK				65
     78 #define CAM_CC_IFE_LITE_1_CLK_SRC			66
     79 #define CAM_CC_IFE_LITE_1_CPHY_RX_CLK			67
     80 #define CAM_CC_IFE_LITE_1_CSID_CLK			68
     81 #define CAM_CC_IFE_LITE_1_CSID_CLK_SRC			69
     82 #define CAM_CC_IPE_0_AHB_CLK				70
     83 #define CAM_CC_IPE_0_AREG_CLK				71
     84 #define CAM_CC_IPE_0_AXI_CLK				72
     85 #define CAM_CC_IPE_0_CLK				73
     86 #define CAM_CC_IPE_0_CLK_SRC				74
     87 #define CAM_CC_IPE_1_AHB_CLK				75
     88 #define CAM_CC_IPE_1_AREG_CLK				76
     89 #define CAM_CC_IPE_1_AXI_CLK				77
     90 #define CAM_CC_IPE_1_CLK				78
     91 #define CAM_CC_JPEG_CLK					79
     92 #define CAM_CC_JPEG_CLK_SRC				80
     93 #define CAM_CC_LRME_CLK					81
     94 #define CAM_CC_LRME_CLK_SRC				82
     95 #define CAM_CC_MCLK0_CLK				83
     96 #define CAM_CC_MCLK0_CLK_SRC				84
     97 #define CAM_CC_MCLK1_CLK				85
     98 #define CAM_CC_MCLK1_CLK_SRC				86
     99 #define CAM_CC_MCLK2_CLK				87
    100 #define CAM_CC_MCLK2_CLK_SRC				88
    101 #define CAM_CC_MCLK3_CLK				89
    102 #define CAM_CC_MCLK3_CLK_SRC				90
    103 #define CAM_CC_SLOW_AHB_CLK_SRC				91
    104 
    105 /* CAM_CC power domains */
    106 #define TITAN_TOP_GDSC					0
    107 #define BPS_GDSC					1
    108 #define IFE_0_GDSC					2
    109 #define IFE_1_GDSC					3
    110 #define IPE_0_GDSC					4
    111 #define IPE_1_GDSC					5
    112 
    113 /* CAM_CC resets */
    114 #define CAM_CC_BPS_BCR					0
    115 #define CAM_CC_CAMNOC_BCR				1
    116 #define CAM_CC_CCI_BCR					2
    117 #define CAM_CC_CPAS_BCR					3
    118 #define CAM_CC_CSI0PHY_BCR				4
    119 #define CAM_CC_CSI1PHY_BCR				5
    120 #define CAM_CC_CSI2PHY_BCR				6
    121 #define CAM_CC_CSI3PHY_BCR				7
    122 #define CAM_CC_FD_BCR					8
    123 #define CAM_CC_ICP_BCR					9
    124 #define CAM_CC_IFE_0_BCR				10
    125 #define CAM_CC_IFE_1_BCR				11
    126 #define CAM_CC_IFE_LITE_0_BCR				12
    127 #define CAM_CC_IFE_LITE_1_BCR				13
    128 #define CAM_CC_IPE_0_BCR				14
    129 #define CAM_CC_IPE_1_BCR				15
    130 #define CAM_CC_JPEG_BCR					16
    131 #define CAM_CC_LRME_BCR					17
    132 #define CAM_CC_MCLK0_BCR				18
    133 #define CAM_CC_MCLK1_BCR				19
    134 #define CAM_CC_MCLK2_BCR				20
    135 #define CAM_CC_MCLK3_BCR				21
    136 
    137 #endif
    138