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      1 /*	$NetBSD: r8a77965-cpg-mssr.h,v 1.1.1.1 2018/04/28 18:25:53 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  * Copyright (C) 2018 Jacopo Mondi <jacopo+renesas (at) jmondi.org>
      6  */
      7 #ifndef __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
      8 #define __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__
      9 
     10 #include <dt-bindings/clock/renesas-cpg-mssr.h>
     11 
     12 /* r8a77965 CPG Core Clocks */
     13 #define R8A77965_CLK_Z			0
     14 #define R8A77965_CLK_ZR			1
     15 #define R8A77965_CLK_ZG			2
     16 #define R8A77965_CLK_ZTR		3
     17 #define R8A77965_CLK_ZTRD2		4
     18 #define R8A77965_CLK_ZT			5
     19 #define R8A77965_CLK_ZX			6
     20 #define R8A77965_CLK_S0D1		7
     21 #define R8A77965_CLK_S0D2		8
     22 #define R8A77965_CLK_S0D3		9
     23 #define R8A77965_CLK_S0D4		10
     24 #define R8A77965_CLK_S0D6		11
     25 #define R8A77965_CLK_S0D8		12
     26 #define R8A77965_CLK_S0D12		13
     27 #define R8A77965_CLK_S1D1		14
     28 #define R8A77965_CLK_S1D2		15
     29 #define R8A77965_CLK_S1D4		16
     30 #define R8A77965_CLK_S2D1		17
     31 #define R8A77965_CLK_S2D2		18
     32 #define R8A77965_CLK_S2D4		19
     33 #define R8A77965_CLK_S3D1		20
     34 #define R8A77965_CLK_S3D2		21
     35 #define R8A77965_CLK_S3D4		22
     36 #define R8A77965_CLK_LB			23
     37 #define R8A77965_CLK_CL			24
     38 #define R8A77965_CLK_ZB3		25
     39 #define R8A77965_CLK_ZB3D2		26
     40 #define R8A77965_CLK_CR			27
     41 #define R8A77965_CLK_CRD2		28
     42 #define R8A77965_CLK_SD0H		29
     43 #define R8A77965_CLK_SD0		30
     44 #define R8A77965_CLK_SD1H		31
     45 #define R8A77965_CLK_SD1		32
     46 #define R8A77965_CLK_SD2H		33
     47 #define R8A77965_CLK_SD2		34
     48 #define R8A77965_CLK_SD3H		35
     49 #define R8A77965_CLK_SD3		36
     50 #define R8A77965_CLK_SSP2		37
     51 #define R8A77965_CLK_SSP1		38
     52 #define R8A77965_CLK_SSPRS		39
     53 #define R8A77965_CLK_RPC		40
     54 #define R8A77965_CLK_RPCD2		41
     55 #define R8A77965_CLK_MSO		42
     56 #define R8A77965_CLK_CANFD		43
     57 #define R8A77965_CLK_HDMI		44
     58 #define R8A77965_CLK_CSI0		45
     59 #define R8A77965_CLK_CP			46
     60 #define R8A77965_CLK_CPEX		47
     61 #define R8A77965_CLK_R			48
     62 #define R8A77965_CLK_OSC		49
     63 
     64 #endif /* __DT_BINDINGS_CLOCK_R8A77965_CPG_MSSR_H__ */
     65