1 /* $NetBSD: rk3128-cru.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright (c) 2017 Rockchip Electronics Co. Ltd. 6 * Author: Elaine <zhangqing (at) rock-chips.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 10 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3128_H 11 12 /* core clocks */ 13 #define PLL_APLL 1 14 #define PLL_DPLL 2 15 #define PLL_CPLL 3 16 #define PLL_GPLL 4 17 #define ARMCLK 5 18 #define PLL_GPLL_DIV2 6 19 #define PLL_GPLL_DIV3 7 20 21 /* sclk gates (special clocks) */ 22 #define SCLK_SPI0 65 23 #define SCLK_NANDC 67 24 #define SCLK_SDMMC 68 25 #define SCLK_SDIO 69 26 #define SCLK_EMMC 71 27 #define SCLK_UART0 77 28 #define SCLK_UART1 78 29 #define SCLK_UART2 79 30 #define SCLK_I2S0 80 31 #define SCLK_I2S1 81 32 #define SCLK_SPDIF 83 33 #define SCLK_TIMER0 85 34 #define SCLK_TIMER1 86 35 #define SCLK_TIMER2 87 36 #define SCLK_TIMER3 88 37 #define SCLK_TIMER4 89 38 #define SCLK_TIMER5 90 39 #define SCLK_SARADC 91 40 #define SCLK_I2S_OUT 113 41 #define SCLK_SDMMC_DRV 114 42 #define SCLK_SDIO_DRV 115 43 #define SCLK_EMMC_DRV 117 44 #define SCLK_SDMMC_SAMPLE 118 45 #define SCLK_SDIO_SAMPLE 119 46 #define SCLK_EMMC_SAMPLE 121 47 #define SCLK_VOP 122 48 #define SCLK_MAC_SRC 124 49 #define SCLK_MAC 126 50 #define SCLK_MAC_REFOUT 127 51 #define SCLK_MAC_REF 128 52 #define SCLK_MAC_RX 129 53 #define SCLK_MAC_TX 130 54 #define SCLK_HEVC_CORE 134 55 #define SCLK_RGA 135 56 #define SCLK_CRYPTO 138 57 #define SCLK_TSP 139 58 #define SCLK_OTGPHY0 142 59 #define SCLK_OTGPHY1 143 60 #define SCLK_DDRC 144 61 #define SCLK_PVTM_FUNC 145 62 #define SCLK_PVTM_CORE 146 63 #define SCLK_PVTM_GPU 147 64 #define SCLK_MIPI_24M 148 65 #define SCLK_PVTM 149 66 #define SCLK_CIF_SRC 150 67 #define SCLK_CIF_OUT_SRC 151 68 #define SCLK_CIF_OUT 152 69 #define SCLK_SFC 153 70 #define SCLK_USB480M 154 71 72 /* dclk gates */ 73 #define DCLK_VOP 190 74 #define DCLK_EBC 191 75 76 /* aclk gates */ 77 #define ACLK_VIO0 192 78 #define ACLK_VIO1 193 79 #define ACLK_DMAC 194 80 #define ACLK_CPU 195 81 #define ACLK_VEPU 196 82 #define ACLK_VDPU 197 83 #define ACLK_CIF 198 84 #define ACLK_IEP 199 85 #define ACLK_LCDC0 204 86 #define ACLK_RGA 205 87 #define ACLK_PERI 210 88 #define ACLK_VOP 211 89 #define ACLK_GMAC 212 90 #define ACLK_GPU 213 91 92 /* pclk gates */ 93 #define PCLK_SARADC 318 94 #define PCLK_WDT 319 95 #define PCLK_GPIO0 320 96 #define PCLK_GPIO1 321 97 #define PCLK_GPIO2 322 98 #define PCLK_GPIO3 323 99 #define PCLK_VIO_H2P 324 100 #define PCLK_MIPI 325 101 #define PCLK_EFUSE 326 102 #define PCLK_HDMI 327 103 #define PCLK_ACODEC 328 104 #define PCLK_GRF 329 105 #define PCLK_I2C0 332 106 #define PCLK_I2C1 333 107 #define PCLK_I2C2 334 108 #define PCLK_I2C3 335 109 #define PCLK_SPI0 338 110 #define PCLK_UART0 341 111 #define PCLK_UART1 342 112 #define PCLK_UART2 343 113 #define PCLK_TSADC 344 114 #define PCLK_PWM 350 115 #define PCLK_TIMER 353 116 #define PCLK_CPU 354 117 #define PCLK_PERI 363 118 #define PCLK_GMAC 367 119 #define PCLK_PMU_PRE 368 120 #define PCLK_SIM_CARD 369 121 122 /* hclk gates */ 123 #define HCLK_SPDIF 440 124 #define HCLK_GPS 441 125 #define HCLK_USBHOST 442 126 #define HCLK_I2S_8CH 443 127 #define HCLK_I2S_2CH 444 128 #define HCLK_VOP 452 129 #define HCLK_NANDC 453 130 #define HCLK_SDMMC 456 131 #define HCLK_SDIO 457 132 #define HCLK_EMMC 459 133 #define HCLK_CPU 460 134 #define HCLK_VEPU 461 135 #define HCLK_VDPU 462 136 #define HCLK_LCDC0 463 137 #define HCLK_EBC 465 138 #define HCLK_VIO 466 139 #define HCLK_RGA 467 140 #define HCLK_IEP 468 141 #define HCLK_VIO_H2P 469 142 #define HCLK_CIF 470 143 #define HCLK_HOST2 473 144 #define HCLK_OTG 474 145 #define HCLK_TSP 475 146 #define HCLK_CRYPTO 476 147 #define HCLK_PERI 478 148 149 #define CLK_NR_CLKS (HCLK_PERI + 1) 150 151 /* soft-reset indices */ 152 #define SRST_CORE0_PO 0 153 #define SRST_CORE1_PO 1 154 #define SRST_CORE2_PO 2 155 #define SRST_CORE3_PO 3 156 #define SRST_CORE0 4 157 #define SRST_CORE1 5 158 #define SRST_CORE2 6 159 #define SRST_CORE3 7 160 #define SRST_CORE0_DBG 8 161 #define SRST_CORE1_DBG 9 162 #define SRST_CORE2_DBG 10 163 #define SRST_CORE3_DBG 11 164 #define SRST_TOPDBG 12 165 #define SRST_ACLK_CORE 13 166 #define SRST_STRC_SYS_A 14 167 #define SRST_L2C 15 168 169 #define SRST_CPUSYS_H 18 170 #define SRST_AHB2APBSYS_H 19 171 #define SRST_SPDIF 20 172 #define SRST_INTMEM 21 173 #define SRST_ROM 22 174 #define SRST_PERI_NIU 23 175 #define SRST_I2S_2CH 24 176 #define SRST_I2S_8CH 25 177 #define SRST_GPU_PVTM 26 178 #define SRST_FUNC_PVTM 27 179 #define SRST_CORE_PVTM 29 180 #define SRST_EFUSE_P 30 181 #define SRST_ACODEC_P 31 182 183 #define SRST_GPIO0 32 184 #define SRST_GPIO1 33 185 #define SRST_GPIO2 34 186 #define SRST_GPIO3 35 187 #define SRST_MIPIPHY_P 36 188 #define SRST_UART0 39 189 #define SRST_UART1 40 190 #define SRST_UART2 41 191 #define SRST_I2C0 43 192 #define SRST_I2C1 44 193 #define SRST_I2C2 45 194 #define SRST_I2C3 46 195 #define SRST_SFC 47 196 197 #define SRST_PWM 48 198 #define SRST_DAP_PO 50 199 #define SRST_DAP 51 200 #define SRST_DAP_SYS 52 201 #define SRST_CRYPTO 53 202 #define SRST_GRF 55 203 #define SRST_GMAC 56 204 #define SRST_PERIPH_SYS_A 57 205 #define SRST_PERIPH_SYS_H 58 206 #define SRST_PERIPH_SYS_P 59 207 #define SRST_SMART_CARD 60 208 #define SRST_CPU_PERI 61 209 #define SRST_EMEM_PERI 62 210 #define SRST_USB_PERI 63 211 212 #define SRST_DMA 64 213 #define SRST_GPS 67 214 #define SRST_NANDC 68 215 #define SRST_USBOTG0 69 216 #define SRST_OTGC0 71 217 #define SRST_USBOTG1 72 218 #define SRST_OTGC1 74 219 #define SRST_DDRMSCH 79 220 221 #define SRST_SDMMC 81 222 #define SRST_SDIO 82 223 #define SRST_EMMC 83 224 #define SRST_SPI 84 225 #define SRST_WDT 86 226 #define SRST_SARADC 87 227 #define SRST_DDRPHY 88 228 #define SRST_DDRPHY_P 89 229 #define SRST_DDRCTRL 90 230 #define SRST_DDRCTRL_P 91 231 #define SRST_TSP 92 232 #define SRST_TSP_CLKIN 93 233 #define SRST_HOST0_ECHI 94 234 235 #define SRST_HDMI_P 96 236 #define SRST_VIO_ARBI_H 97 237 #define SRST_VIO0_A 98 238 #define SRST_VIO_BUS_H 99 239 #define SRST_VOP_A 100 240 #define SRST_VOP_H 101 241 #define SRST_VOP_D 102 242 #define SRST_UTMI0 103 243 #define SRST_UTMI1 104 244 #define SRST_USBPOR 105 245 #define SRST_IEP_A 106 246 #define SRST_IEP_H 107 247 #define SRST_RGA_A 108 248 #define SRST_RGA_H 109 249 #define SRST_CIF0 110 250 #define SRST_PMU 111 251 252 #define SRST_VCODEC_A 112 253 #define SRST_VCODEC_H 113 254 #define SRST_VIO1_A 114 255 #define SRST_HEVC_CORE 115 256 #define SRST_VCODEC_NIU_A 116 257 #define SRST_PMU_NIU_P 117 258 #define SRST_LCDC0_S 119 259 #define SRST_GPU 120 260 #define SRST_GPU_NIU_A 122 261 #define SRST_EBC_A 123 262 #define SRST_EBC_H 124 263 264 #define SRST_CORE_DBG 128 265 #define SRST_DBG_P 129 266 #define SRST_TIMER0 130 267 #define SRST_TIMER1 131 268 #define SRST_TIMER2 132 269 #define SRST_TIMER3 133 270 #define SRST_TIMER4 134 271 #define SRST_TIMER5 135 272 #define SRST_VIO_H2P 136 273 #define SRST_VIO_MIPI_DSI 137 274 275 #endif 276
Indexes created Mon Sep 29 21:09:56 GMT 2025