1 /* $NetBSD: rk3188-cru-common.h,v 1.1.1.4 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright (c) 2014 MundoReader S.L. 6 * Author: Heiko Stuebner <heiko (at) sntech.de> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H 10 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H 11 12 /* core clocks from */ 13 #define PLL_APLL 1 14 #define PLL_DPLL 2 15 #define PLL_CPLL 3 16 #define PLL_GPLL 4 17 #define CORE_PERI 5 18 #define CORE_L2C 6 19 #define ARMCLK 7 20 21 /* sclk gates (special clocks) */ 22 #define SCLK_UART0 64 23 #define SCLK_UART1 65 24 #define SCLK_UART2 66 25 #define SCLK_UART3 67 26 #define SCLK_MAC 68 27 #define SCLK_SPI0 69 28 #define SCLK_SPI1 70 29 #define SCLK_SARADC 71 30 #define SCLK_SDMMC 72 31 #define SCLK_SDIO 73 32 #define SCLK_EMMC 74 33 #define SCLK_I2S0 75 34 #define SCLK_I2S1 76 35 #define SCLK_I2S2 77 36 #define SCLK_SPDIF 78 37 #define SCLK_CIF0 79 38 #define SCLK_CIF1 80 39 #define SCLK_OTGPHY0 81 40 #define SCLK_OTGPHY1 82 41 #define SCLK_HSADC 83 42 #define SCLK_TIMER0 84 43 #define SCLK_TIMER1 85 44 #define SCLK_TIMER2 86 45 #define SCLK_TIMER3 87 46 #define SCLK_TIMER4 88 47 #define SCLK_TIMER5 89 48 #define SCLK_TIMER6 90 49 #define SCLK_JTAG 91 50 #define SCLK_SMC 92 51 #define SCLK_TSADC 93 52 53 #define DCLK_LCDC0 190 54 #define DCLK_LCDC1 191 55 56 /* aclk gates */ 57 #define ACLK_DMA1 192 58 #define ACLK_DMA2 193 59 #define ACLK_GPS 194 60 #define ACLK_LCDC0 195 61 #define ACLK_LCDC1 196 62 #define ACLK_GPU 197 63 #define ACLK_SMC 198 64 #define ACLK_CIF1 199 65 #define ACLK_IPP 200 66 #define ACLK_RGA 201 67 #define ACLK_CIF0 202 68 #define ACLK_CPU 203 69 #define ACLK_PERI 204 70 #define ACLK_VEPU 205 71 #define ACLK_VDPU 206 72 73 /* pclk gates */ 74 #define PCLK_GRF 320 75 #define PCLK_PMU 321 76 #define PCLK_TIMER0 322 77 #define PCLK_TIMER1 323 78 #define PCLK_TIMER2 324 79 #define PCLK_TIMER3 325 80 #define PCLK_PWM01 326 81 #define PCLK_PWM23 327 82 #define PCLK_SPI0 328 83 #define PCLK_SPI1 329 84 #define PCLK_SARADC 330 85 #define PCLK_WDT 331 86 #define PCLK_UART0 332 87 #define PCLK_UART1 333 88 #define PCLK_UART2 334 89 #define PCLK_UART3 335 90 #define PCLK_I2C0 336 91 #define PCLK_I2C1 337 92 #define PCLK_I2C2 338 93 #define PCLK_I2C3 339 94 #define PCLK_I2C4 340 95 #define PCLK_GPIO0 341 96 #define PCLK_GPIO1 342 97 #define PCLK_GPIO2 343 98 #define PCLK_GPIO3 344 99 #define PCLK_GPIO4 345 100 #define PCLK_GPIO6 346 101 #define PCLK_EFUSE 347 102 #define PCLK_TZPC 348 103 #define PCLK_TSADC 349 104 #define PCLK_CPU 350 105 #define PCLK_PERI 351 106 #define PCLK_DDRUPCTL 352 107 #define PCLK_PUBL 353 108 109 /* hclk gates */ 110 #define HCLK_SDMMC 448 111 #define HCLK_SDIO 449 112 #define HCLK_EMMC 450 113 #define HCLK_OTG0 451 114 #define HCLK_EMAC 452 115 #define HCLK_SPDIF 453 116 #define HCLK_I2S0 454 117 #define HCLK_I2S1 455 118 #define HCLK_I2S2 456 119 #define HCLK_OTG1 457 120 #define HCLK_HSIC 458 121 #define HCLK_HSADC 459 122 #define HCLK_PIDF 460 123 #define HCLK_LCDC0 461 124 #define HCLK_LCDC1 462 125 #define HCLK_ROM 463 126 #define HCLK_CIF0 464 127 #define HCLK_IPP 465 128 #define HCLK_RGA 466 129 #define HCLK_NANDC0 467 130 #define HCLK_CPU 468 131 #define HCLK_PERI 469 132 #define HCLK_CIF1 470 133 #define HCLK_VEPU 471 134 #define HCLK_VDPU 472 135 #define HCLK_HDMI 473 136 137 #define CLK_NR_CLKS (HCLK_HDMI + 1) 138 139 /* soft-reset indices */ 140 #define SRST_MCORE 2 141 #define SRST_CORE0 3 142 #define SRST_CORE1 4 143 #define SRST_MCORE_DBG 7 144 #define SRST_CORE0_DBG 8 145 #define SRST_CORE1_DBG 9 146 #define SRST_CORE0_WDT 12 147 #define SRST_CORE1_WDT 13 148 #define SRST_STRC_SYS 14 149 #define SRST_L2C 15 150 151 #define SRST_CPU_AHB 17 152 #define SRST_AHB2APB 19 153 #define SRST_DMA1 20 154 #define SRST_INTMEM 21 155 #define SRST_ROM 22 156 #define SRST_SPDIF 26 157 #define SRST_TIMER0 27 158 #define SRST_TIMER1 28 159 #define SRST_EFUSE 30 160 161 #define SRST_GPIO0 32 162 #define SRST_GPIO1 33 163 #define SRST_GPIO2 34 164 #define SRST_GPIO3 35 165 166 #define SRST_UART0 39 167 #define SRST_UART1 40 168 #define SRST_UART2 41 169 #define SRST_UART3 42 170 #define SRST_I2C0 43 171 #define SRST_I2C1 44 172 #define SRST_I2C2 45 173 #define SRST_I2C3 46 174 #define SRST_I2C4 47 175 176 #define SRST_PWM0 48 177 #define SRST_PWM1 49 178 #define SRST_DAP_PO 50 179 #define SRST_DAP 51 180 #define SRST_DAP_SYS 52 181 #define SRST_TPIU_ATB 53 182 #define SRST_PMU_APB 54 183 #define SRST_GRF 55 184 #define SRST_PMU 56 185 #define SRST_PERI_AXI 57 186 #define SRST_PERI_AHB 58 187 #define SRST_PERI_APB 59 188 #define SRST_PERI_NIU 60 189 #define SRST_CPU_PERI 61 190 #define SRST_EMEM_PERI 62 191 #define SRST_USB_PERI 63 192 193 #define SRST_DMA2 64 194 #define SRST_SMC 65 195 #define SRST_MAC 66 196 #define SRST_NANC0 68 197 #define SRST_USBOTG0 69 198 #define SRST_USBPHY0 70 199 #define SRST_OTGC0 71 200 #define SRST_USBOTG1 72 201 #define SRST_USBPHY1 73 202 #define SRST_OTGC1 74 203 #define SRST_HSADC 76 204 #define SRST_PIDFILTER 77 205 #define SRST_DDR_MSCH 79 206 207 #define SRST_TZPC 80 208 #define SRST_SDMMC 81 209 #define SRST_SDIO 82 210 #define SRST_EMMC 83 211 #define SRST_SPI0 84 212 #define SRST_SPI1 85 213 #define SRST_WDT 86 214 #define SRST_SARADC 87 215 #define SRST_DDRPHY 88 216 #define SRST_DDRPHY_APB 89 217 #define SRST_DDRCTL 90 218 #define SRST_DDRCTL_APB 91 219 #define SRST_DDRPUB 93 220 221 #define SRST_VIO0_AXI 98 222 #define SRST_VIO0_AHB 99 223 #define SRST_LCDC0_AXI 100 224 #define SRST_LCDC0_AHB 101 225 #define SRST_LCDC0_DCLK 102 226 #define SRST_LCDC1_AXI 103 227 #define SRST_LCDC1_AHB 104 228 #define SRST_LCDC1_DCLK 105 229 #define SRST_IPP_AXI 106 230 #define SRST_IPP_AHB 107 231 #define SRST_RGA_AXI 108 232 #define SRST_RGA_AHB 109 233 #define SRST_CIF0 110 234 235 #define SRST_VCODEC_AXI 112 236 #define SRST_VCODEC_AHB 113 237 #define SRST_VIO1_AXI 114 238 #define SRST_VCODEC_CPU 115 239 #define SRST_VCODEC_NIU 116 240 #define SRST_GPU 120 241 #define SRST_GPU_NIU 122 242 #define SRST_TFUN_ATB 125 243 #define SRST_TFUN_APB 126 244 #define SRST_CTI4_APB 127 245 246 #define SRST_TPIU_APB 128 247 #define SRST_TRACE 129 248 #define SRST_CORE_DBG 130 249 #define SRST_DBG_APB 131 250 #define SRST_CTI0 132 251 #define SRST_CTI0_APB 133 252 #define SRST_CTI1 134 253 #define SRST_CTI1_APB 135 254 #define SRST_PTM_CORE0 136 255 #define SRST_PTM_CORE1 137 256 #define SRST_PTM0 138 257 #define SRST_PTM0_ATB 139 258 #define SRST_PTM1 140 259 #define SRST_PTM1_ATB 141 260 #define SRST_CTM 142 261 #define SRST_TS 143 262 263 #endif 264
Indexes created Mon Sep 29 03:10:08 GMT 2025