1 /* $NetBSD: rk3228-cru.h,v 1.1.1.3 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright (c) 2015 Rockchip Electronics Co. Ltd. 6 * Author: Jeffy Chen <jeffy.chen (at) rock-chips.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 10 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H 11 12 /* core clocks */ 13 #define PLL_APLL 1 14 #define PLL_DPLL 2 15 #define PLL_CPLL 3 16 #define PLL_GPLL 4 17 #define ARMCLK 5 18 19 /* sclk gates (special clocks) */ 20 #define SCLK_SPI0 65 21 #define SCLK_NANDC 67 22 #define SCLK_SDMMC 68 23 #define SCLK_SDIO 69 24 #define SCLK_EMMC 71 25 #define SCLK_TSADC 72 26 #define SCLK_UART0 77 27 #define SCLK_UART1 78 28 #define SCLK_UART2 79 29 #define SCLK_I2S0 80 30 #define SCLK_I2S1 81 31 #define SCLK_I2S2 82 32 #define SCLK_SPDIF 83 33 #define SCLK_TIMER0 85 34 #define SCLK_TIMER1 86 35 #define SCLK_TIMER2 87 36 #define SCLK_TIMER3 88 37 #define SCLK_TIMER4 89 38 #define SCLK_TIMER5 90 39 #define SCLK_I2S_OUT 113 40 #define SCLK_SDMMC_DRV 114 41 #define SCLK_SDIO_DRV 115 42 #define SCLK_EMMC_DRV 117 43 #define SCLK_SDMMC_SAMPLE 118 44 #define SCLK_SDIO_SAMPLE 119 45 #define SCLK_SDIO_SRC 120 46 #define SCLK_EMMC_SAMPLE 121 47 #define SCLK_VOP 122 48 #define SCLK_HDMI_HDCP 123 49 #define SCLK_MAC_SRC 124 50 #define SCLK_MAC_EXTCLK 125 51 #define SCLK_MAC 126 52 #define SCLK_MAC_REFOUT 127 53 #define SCLK_MAC_REF 128 54 #define SCLK_MAC_RX 129 55 #define SCLK_MAC_TX 130 56 #define SCLK_MAC_PHY 131 57 #define SCLK_MAC_OUT 132 58 #define SCLK_VDEC_CABAC 133 59 #define SCLK_VDEC_CORE 134 60 #define SCLK_RGA 135 61 #define SCLK_HDCP 136 62 #define SCLK_HDMI_CEC 137 63 #define SCLK_CRYPTO 138 64 #define SCLK_TSP 139 65 #define SCLK_HSADC 140 66 #define SCLK_WIFI 141 67 #define SCLK_OTGPHY0 142 68 #define SCLK_OTGPHY1 143 69 #define SCLK_HDMI_PHY 144 70 71 /* dclk gates */ 72 #define DCLK_VOP 190 73 #define DCLK_HDMI_PHY 191 74 75 /* aclk gates */ 76 #define ACLK_DMAC 194 77 #define ACLK_CPU 195 78 #define ACLK_VPU_PRE 196 79 #define ACLK_RKVDEC_PRE 197 80 #define ACLK_RGA_PRE 198 81 #define ACLK_IEP_PRE 199 82 #define ACLK_HDCP_PRE 200 83 #define ACLK_VOP_PRE 201 84 #define ACLK_VPU 202 85 #define ACLK_RKVDEC 203 86 #define ACLK_IEP 204 87 #define ACLK_RGA 205 88 #define ACLK_HDCP 206 89 #define ACLK_PERI 210 90 #define ACLK_VOP 211 91 #define ACLK_GMAC 212 92 #define ACLK_GPU 213 93 94 /* pclk gates */ 95 #define PCLK_GPIO0 320 96 #define PCLK_GPIO1 321 97 #define PCLK_GPIO2 322 98 #define PCLK_GPIO3 323 99 #define PCLK_VIO_H2P 324 100 #define PCLK_HDCP 325 101 #define PCLK_EFUSE_1024 326 102 #define PCLK_EFUSE_256 327 103 #define PCLK_GRF 329 104 #define PCLK_I2C0 332 105 #define PCLK_I2C1 333 106 #define PCLK_I2C2 334 107 #define PCLK_I2C3 335 108 #define PCLK_SPI0 338 109 #define PCLK_UART0 341 110 #define PCLK_UART1 342 111 #define PCLK_UART2 343 112 #define PCLK_TSADC 344 113 #define PCLK_PWM 350 114 #define PCLK_TIMER 353 115 #define PCLK_CPU 354 116 #define PCLK_PERI 363 117 #define PCLK_HDMI_CTRL 364 118 #define PCLK_HDMI_PHY 365 119 #define PCLK_GMAC 367 120 121 /* hclk gates */ 122 #define HCLK_I2S0_8CH 442 123 #define HCLK_I2S1_8CH 443 124 #define HCLK_I2S2_2CH 444 125 #define HCLK_SPDIF_8CH 445 126 #define HCLK_VOP 452 127 #define HCLK_NANDC 453 128 #define HCLK_SDMMC 456 129 #define HCLK_SDIO 457 130 #define HCLK_EMMC 459 131 #define HCLK_CPU 460 132 #define HCLK_VPU_PRE 461 133 #define HCLK_RKVDEC_PRE 462 134 #define HCLK_VIO_PRE 463 135 #define HCLK_VPU 464 136 #define HCLK_RKVDEC 465 137 #define HCLK_VIO 466 138 #define HCLK_RGA 467 139 #define HCLK_IEP 468 140 #define HCLK_VIO_H2P 469 141 #define HCLK_HDCP_MMU 470 142 #define HCLK_HOST0 471 143 #define HCLK_HOST1 472 144 #define HCLK_HOST2 473 145 #define HCLK_OTG 474 146 #define HCLK_TSP 475 147 #define HCLK_M_CRYPTO 476 148 #define HCLK_S_CRYPTO 477 149 #define HCLK_PERI 478 150 151 #define CLK_NR_CLKS (HCLK_PERI + 1) 152 153 /* soft-reset indices */ 154 #define SRST_CORE0_PO 0 155 #define SRST_CORE1_PO 1 156 #define SRST_CORE2_PO 2 157 #define SRST_CORE3_PO 3 158 #define SRST_CORE0 4 159 #define SRST_CORE1 5 160 #define SRST_CORE2 6 161 #define SRST_CORE3 7 162 #define SRST_CORE0_DBG 8 163 #define SRST_CORE1_DBG 9 164 #define SRST_CORE2_DBG 10 165 #define SRST_CORE3_DBG 11 166 #define SRST_TOPDBG 12 167 #define SRST_ACLK_CORE 13 168 #define SRST_NOC 14 169 #define SRST_L2C 15 170 171 #define SRST_CPUSYS_H 18 172 #define SRST_BUSSYS_H 19 173 #define SRST_SPDIF 20 174 #define SRST_INTMEM 21 175 #define SRST_ROM 22 176 #define SRST_OTG_ADP 23 177 #define SRST_I2S0 24 178 #define SRST_I2S1 25 179 #define SRST_I2S2 26 180 #define SRST_ACODEC_P 27 181 #define SRST_DFIMON 28 182 #define SRST_MSCH 29 183 #define SRST_EFUSE1024 30 184 #define SRST_EFUSE256 31 185 186 #define SRST_GPIO0 32 187 #define SRST_GPIO1 33 188 #define SRST_GPIO2 34 189 #define SRST_GPIO3 35 190 #define SRST_PERIPH_NOC_A 36 191 #define SRST_PERIPH_NOC_BUS_H 37 192 #define SRST_PERIPH_NOC_P 38 193 #define SRST_UART0 39 194 #define SRST_UART1 40 195 #define SRST_UART2 41 196 #define SRST_PHYNOC 42 197 #define SRST_I2C0 43 198 #define SRST_I2C1 44 199 #define SRST_I2C2 45 200 #define SRST_I2C3 46 201 202 #define SRST_PWM 48 203 #define SRST_A53_GIC 49 204 #define SRST_DAP 51 205 #define SRST_DAP_NOC 52 206 #define SRST_CRYPTO 53 207 #define SRST_SGRF 54 208 #define SRST_GRF 55 209 #define SRST_GMAC 56 210 #define SRST_PERIPH_NOC_H 58 211 #define SRST_MACPHY 63 212 213 #define SRST_DMA 64 214 #define SRST_NANDC 68 215 #define SRST_USBOTG 69 216 #define SRST_OTGC 70 217 #define SRST_USBHOST0 71 218 #define SRST_HOST_CTRL0 72 219 #define SRST_USBHOST1 73 220 #define SRST_HOST_CTRL1 74 221 #define SRST_USBHOST2 75 222 #define SRST_HOST_CTRL2 76 223 #define SRST_USBPOR0 77 224 #define SRST_USBPOR1 78 225 #define SRST_DDRMSCH 79 226 227 #define SRST_SMART_CARD 80 228 #define SRST_SDMMC 81 229 #define SRST_SDIO 82 230 #define SRST_EMMC 83 231 #define SRST_SPI 84 232 #define SRST_TSP_H 85 233 #define SRST_TSP 86 234 #define SRST_TSADC 87 235 #define SRST_DDRPHY 88 236 #define SRST_DDRPHY_P 89 237 #define SRST_DDRCTRL 90 238 #define SRST_DDRCTRL_P 91 239 #define SRST_HOST0_ECHI 92 240 #define SRST_HOST1_ECHI 93 241 #define SRST_HOST2_ECHI 94 242 #define SRST_VOP_NOC_A 95 243 244 #define SRST_HDMI_P 96 245 #define SRST_VIO_ARBI_H 97 246 #define SRST_IEP_NOC_A 98 247 #define SRST_VIO_NOC_H 99 248 #define SRST_VOP_A 100 249 #define SRST_VOP_H 101 250 #define SRST_VOP_D 102 251 #define SRST_UTMI0 103 252 #define SRST_UTMI1 104 253 #define SRST_UTMI2 105 254 #define SRST_UTMI3 106 255 #define SRST_RGA 107 256 #define SRST_RGA_NOC_A 108 257 #define SRST_RGA_A 109 258 #define SRST_RGA_H 110 259 #define SRST_HDCP_A 111 260 261 #define SRST_VPU_A 112 262 #define SRST_VPU_H 113 263 #define SRST_VPU_NOC_A 116 264 #define SRST_VPU_NOC_H 117 265 #define SRST_RKVDEC_A 118 266 #define SRST_RKVDEC_NOC_A 119 267 #define SRST_RKVDEC_H 120 268 #define SRST_RKVDEC_NOC_H 121 269 #define SRST_RKVDEC_CORE 122 270 #define SRST_RKVDEC_CABAC 123 271 #define SRST_IEP_A 124 272 #define SRST_IEP_H 125 273 #define SRST_GPU_A 126 274 #define SRST_GPU_NOC_A 127 275 276 #define SRST_CORE_DBG 128 277 #define SRST_DBG_P 129 278 #define SRST_TIMER0 130 279 #define SRST_TIMER1 131 280 #define SRST_TIMER2 132 281 #define SRST_TIMER3 133 282 #define SRST_TIMER4 134 283 #define SRST_TIMER5 135 284 #define SRST_VIO_H2P 136 285 #define SRST_HDMIPHY 139 286 #define SRST_VDAC 140 287 #define SRST_TIMER_6CH_P 141 288 289 #endif 290
Indexes created Mon Sep 29 15:09:53 GMT 2025