1 /* $NetBSD: rk3308-cru.h,v 1.1.1.1 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2019 Rockchip Electronics Co. Ltd. 6 * Author: Finley Xiao <finley.xiao (at) rock-chips.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H 10 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3308_H 11 12 /* core clocks */ 13 #define PLL_APLL 1 14 #define PLL_DPLL 2 15 #define PLL_VPLL0 3 16 #define PLL_VPLL1 4 17 #define ARMCLK 5 18 19 /* sclk (special clocks) */ 20 #define USB480M 14 21 #define SCLK_RTC32K 15 22 #define SCLK_PVTM_CORE 16 23 #define SCLK_UART0 17 24 #define SCLK_UART1 18 25 #define SCLK_UART2 19 26 #define SCLK_UART3 20 27 #define SCLK_UART4 21 28 #define SCLK_I2C0 22 29 #define SCLK_I2C1 23 30 #define SCLK_I2C2 24 31 #define SCLK_I2C3 25 32 #define SCLK_PWM0 26 33 #define SCLK_SPI0 27 34 #define SCLK_SPI1 28 35 #define SCLK_SPI2 29 36 #define SCLK_TIMER0 30 37 #define SCLK_TIMER1 31 38 #define SCLK_TIMER2 32 39 #define SCLK_TIMER3 33 40 #define SCLK_TIMER4 34 41 #define SCLK_TIMER5 35 42 #define SCLK_TSADC 36 43 #define SCLK_SARADC 37 44 #define SCLK_OTP 38 45 #define SCLK_OTP_USR 39 46 #define SCLK_CPU_BOOST 40 47 #define SCLK_CRYPTO 41 48 #define SCLK_CRYPTO_APK 42 49 #define SCLK_NANDC_DIV 43 50 #define SCLK_NANDC_DIV50 44 51 #define SCLK_NANDC 45 52 #define SCLK_SDMMC_DIV 46 53 #define SCLK_SDMMC_DIV50 47 54 #define SCLK_SDMMC 48 55 #define SCLK_SDMMC_DRV 49 56 #define SCLK_SDMMC_SAMPLE 50 57 #define SCLK_SDIO_DIV 51 58 #define SCLK_SDIO_DIV50 52 59 #define SCLK_SDIO 53 60 #define SCLK_SDIO_DRV 54 61 #define SCLK_SDIO_SAMPLE 55 62 #define SCLK_EMMC_DIV 56 63 #define SCLK_EMMC_DIV50 57 64 #define SCLK_EMMC 58 65 #define SCLK_EMMC_DRV 59 66 #define SCLK_EMMC_SAMPLE 60 67 #define SCLK_SFC 61 68 #define SCLK_OTG_ADP 62 69 #define SCLK_MAC_SRC 63 70 #define SCLK_MAC 64 71 #define SCLK_MAC_REF 65 72 #define SCLK_MAC_RX_TX 66 73 #define SCLK_MAC_RMII 67 74 #define SCLK_DDR_MON_TIMER 68 75 #define SCLK_DDR_MON 69 76 #define SCLK_DDRCLK 70 77 #define SCLK_PMU 71 78 #define SCLK_USBPHY_REF 72 79 #define SCLK_WIFI 73 80 #define SCLK_PVTM_PMU 74 81 #define SCLK_PDM 75 82 #define SCLK_I2S0_8CH_TX 76 83 #define SCLK_I2S0_8CH_TX_OUT 77 84 #define SCLK_I2S0_8CH_RX 78 85 #define SCLK_I2S0_8CH_RX_OUT 79 86 #define SCLK_I2S1_8CH_TX 80 87 #define SCLK_I2S1_8CH_TX_OUT 81 88 #define SCLK_I2S1_8CH_RX 82 89 #define SCLK_I2S1_8CH_RX_OUT 83 90 #define SCLK_I2S2_8CH_TX 84 91 #define SCLK_I2S2_8CH_TX_OUT 85 92 #define SCLK_I2S2_8CH_RX 86 93 #define SCLK_I2S2_8CH_RX_OUT 87 94 #define SCLK_I2S3_8CH_TX 88 95 #define SCLK_I2S3_8CH_TX_OUT 89 96 #define SCLK_I2S3_8CH_RX 90 97 #define SCLK_I2S3_8CH_RX_OUT 91 98 #define SCLK_I2S0_2CH 92 99 #define SCLK_I2S0_2CH_OUT 93 100 #define SCLK_I2S1_2CH 94 101 #define SCLK_I2S1_2CH_OUT 95 102 #define SCLK_SPDIF_TX_DIV 96 103 #define SCLK_SPDIF_TX_DIV50 97 104 #define SCLK_SPDIF_TX 98 105 #define SCLK_SPDIF_RX_DIV 99 106 #define SCLK_SPDIF_RX_DIV50 100 107 #define SCLK_SPDIF_RX 101 108 #define SCLK_I2S0_8CH_TX_MUX 102 109 #define SCLK_I2S0_8CH_RX_MUX 103 110 #define SCLK_I2S1_8CH_TX_MUX 104 111 #define SCLK_I2S1_8CH_RX_MUX 105 112 #define SCLK_I2S2_8CH_TX_MUX 106 113 #define SCLK_I2S2_8CH_RX_MUX 107 114 #define SCLK_I2S3_8CH_TX_MUX 108 115 #define SCLK_I2S3_8CH_RX_MUX 109 116 #define SCLK_I2S0_8CH_TX_SRC 110 117 #define SCLK_I2S0_8CH_RX_SRC 111 118 #define SCLK_I2S1_8CH_TX_SRC 112 119 #define SCLK_I2S1_8CH_RX_SRC 113 120 #define SCLK_I2S2_8CH_TX_SRC 114 121 #define SCLK_I2S2_8CH_RX_SRC 115 122 #define SCLK_I2S3_8CH_TX_SRC 116 123 #define SCLK_I2S3_8CH_RX_SRC 117 124 #define SCLK_I2S0_2CH_SRC 118 125 #define SCLK_I2S1_2CH_SRC 119 126 #define SCLK_PWM1 120 127 #define SCLK_PWM2 121 128 #define SCLK_OWIRE 122 129 130 /* dclk */ 131 #define DCLK_VOP 125 132 133 /* aclk */ 134 #define ACLK_BUS_SRC 130 135 #define ACLK_BUS 131 136 #define ACLK_PERI_SRC 132 137 #define ACLK_PERI 133 138 #define ACLK_MAC 134 139 #define ACLK_CRYPTO 135 140 #define ACLK_VOP 136 141 #define ACLK_GIC 137 142 #define ACLK_DMAC0 138 143 #define ACLK_DMAC1 139 144 145 /* hclk */ 146 #define HCLK_BUS 150 147 #define HCLK_PERI 151 148 #define HCLK_AUDIO 152 149 #define HCLK_NANDC 153 150 #define HCLK_SDMMC 154 151 #define HCLK_SDIO 155 152 #define HCLK_EMMC 156 153 #define HCLK_SFC 157 154 #define HCLK_OTG 158 155 #define HCLK_HOST 159 156 #define HCLK_HOST_ARB 160 157 #define HCLK_PDM 161 158 #define HCLK_SPDIFTX 162 159 #define HCLK_SPDIFRX 163 160 #define HCLK_I2S0_8CH 164 161 #define HCLK_I2S1_8CH 165 162 #define HCLK_I2S2_8CH 166 163 #define HCLK_I2S3_8CH 167 164 #define HCLK_I2S0_2CH 168 165 #define HCLK_I2S1_2CH 169 166 #define HCLK_VAD 170 167 #define HCLK_CRYPTO 171 168 #define HCLK_VOP 172 169 170 /* pclk */ 171 #define PCLK_BUS 190 172 #define PCLK_DDR 191 173 #define PCLK_PERI 192 174 #define PCLK_PMU 193 175 #define PCLK_AUDIO 194 176 #define PCLK_MAC 195 177 #define PCLK_ACODEC 196 178 #define PCLK_UART0 197 179 #define PCLK_UART1 198 180 #define PCLK_UART2 199 181 #define PCLK_UART3 200 182 #define PCLK_UART4 201 183 #define PCLK_I2C0 202 184 #define PCLK_I2C1 203 185 #define PCLK_I2C2 204 186 #define PCLK_I2C3 205 187 #define PCLK_PWM0 206 188 #define PCLK_SPI0 207 189 #define PCLK_SPI1 208 190 #define PCLK_SPI2 209 191 #define PCLK_SARADC 210 192 #define PCLK_TSADC 211 193 #define PCLK_TIMER 212 194 #define PCLK_OTP_NS 213 195 #define PCLK_WDT 214 196 #define PCLK_GPIO0 215 197 #define PCLK_GPIO1 216 198 #define PCLK_GPIO2 217 199 #define PCLK_GPIO3 218 200 #define PCLK_GPIO4 219 201 #define PCLK_SGRF 220 202 #define PCLK_GRF 221 203 #define PCLK_USBSD_DET 222 204 #define PCLK_DDR_UPCTL 223 205 #define PCLK_DDR_MON 224 206 #define PCLK_DDRPHY 225 207 #define PCLK_DDR_STDBY 226 208 #define PCLK_USB_GRF 227 209 #define PCLK_CRU 228 210 #define PCLK_OTP_PHY 229 211 #define PCLK_CPU_BOOST 230 212 #define PCLK_PWM1 231 213 #define PCLK_PWM2 232 214 #define PCLK_CAN 233 215 #define PCLK_OWIRE 234 216 217 #define CLK_NR_CLKS (PCLK_OWIRE + 1) 218 219 /* soft-reset indices */ 220 221 /* cru_softrst_con0 */ 222 #define SRST_CORE0_PO 0 223 #define SRST_CORE1_PO 1 224 #define SRST_CORE2_PO 2 225 #define SRST_CORE3_PO 3 226 #define SRST_CORE0 4 227 #define SRST_CORE1 5 228 #define SRST_CORE2 6 229 #define SRST_CORE3 7 230 #define SRST_CORE0_DBG 8 231 #define SRST_CORE1_DBG 9 232 #define SRST_CORE2_DBG 10 233 #define SRST_CORE3_DBG 11 234 #define SRST_TOPDBG 12 235 #define SRST_CORE_NOC 13 236 #define SRST_STRC_A 14 237 #define SRST_L2C 15 238 239 /* cru_softrst_con1 */ 240 #define SRST_DAP 16 241 #define SRST_CORE_PVTM 17 242 #define SRST_CORE_PRF 18 243 #define SRST_CORE_GRF 19 244 #define SRST_DDRUPCTL 20 245 #define SRST_DDRUPCTL_P 22 246 #define SRST_MSCH 23 247 #define SRST_DDRMON_P 25 248 #define SRST_DDRSTDBY_P 26 249 #define SRST_DDRSTDBY 27 250 #define SRST_DDRPHY 28 251 #define SRST_DDRPHY_DIV 29 252 #define SRST_DDRPHY_P 30 253 254 /* cru_softrst_con2 */ 255 #define SRST_BUS_NIU_H 32 256 #define SRST_USB_NIU_P 33 257 #define SRST_CRYPTO_A 34 258 #define SRST_CRYPTO_H 35 259 #define SRST_CRYPTO 36 260 #define SRST_CRYPTO_APK 37 261 #define SRST_VOP_A 38 262 #define SRST_VOP_H 39 263 #define SRST_VOP_D 40 264 #define SRST_INTMEM_A 41 265 #define SRST_ROM_H 42 266 #define SRST_GIC_A 43 267 #define SRST_UART0_P 44 268 #define SRST_UART0 45 269 #define SRST_UART1_P 46 270 #define SRST_UART1 47 271 272 /* cru_softrst_con3 */ 273 #define SRST_UART2_P 48 274 #define SRST_UART2 49 275 #define SRST_UART3_P 50 276 #define SRST_UART3 51 277 #define SRST_UART4_P 52 278 #define SRST_UART4 53 279 #define SRST_I2C0_P 54 280 #define SRST_I2C0 55 281 #define SRST_I2C1_P 56 282 #define SRST_I2C1 57 283 #define SRST_I2C2_P 58 284 #define SRST_I2C2 59 285 #define SRST_I2C3_P 60 286 #define SRST_I2C3 61 287 #define SRST_PWM0_P 62 288 #define SRST_PWM0 63 289 290 /* cru_softrst_con4 */ 291 #define SRST_SPI0_P 64 292 #define SRST_SPI0 65 293 #define SRST_SPI1_P 66 294 #define SRST_SPI1 67 295 #define SRST_SPI2_P 68 296 #define SRST_SPI2 69 297 #define SRST_SARADC_P 70 298 #define SRST_TSADC_P 71 299 #define SRST_TSADC 72 300 #define SRST_TIMER0_P 73 301 #define SRST_TIMER0 74 302 #define SRST_TIMER1 75 303 #define SRST_TIMER2 76 304 #define SRST_TIMER3 77 305 #define SRST_TIMER4 78 306 #define SRST_TIMER5 79 307 308 /* cru_softrst_con5 */ 309 #define SRST_OTP_NS_P 80 310 #define SRST_OTP_NS_SBPI 81 311 #define SRST_OTP_NS_USR 82 312 #define SRST_OTP_PHY_P 83 313 #define SRST_OTP_PHY 84 314 #define SRST_GPIO0_P 86 315 #define SRST_GPIO1_P 87 316 #define SRST_GPIO2_P 88 317 #define SRST_GPIO3_P 89 318 #define SRST_GPIO4_P 90 319 #define SRST_GRF_P 91 320 #define SRST_USBSD_DET_P 92 321 #define SRST_PMU 93 322 #define SRST_PMU_PVTM 94 323 #define SRST_USB_GRF_P 95 324 325 /* cru_softrst_con6 */ 326 #define SRST_CPU_BOOST 96 327 #define SRST_CPU_BOOST_P 97 328 #define SRST_PWM1_P 98 329 #define SRST_PWM1 99 330 #define SRST_PWM2_P 100 331 #define SRST_PWM2 101 332 #define SRST_PERI_NIU_A 104 333 #define SRST_PERI_NIU_H 105 334 #define SRST_PERI_NIU_p 106 335 #define SRST_USB2OTG_H 107 336 #define SRST_USB2OTG 108 337 #define SRST_USB2OTG_ADP 109 338 #define SRST_USB2HOST_H 110 339 #define SRST_USB2HOST_ARB_H 111 340 341 /* cru_softrst_con7 */ 342 #define SRST_USB2HOST_AUX_H 112 343 #define SRST_USB2HOST_EHCI 113 344 #define SRST_USB2HOST 114 345 #define SRST_USBPHYPOR 115 346 #define SRST_UTMI0 116 347 #define SRST_UTMI1 117 348 #define SRST_SDIO_H 118 349 #define SRST_EMMC_H 119 350 #define SRST_SFC_H 120 351 #define SRST_SFC 121 352 #define SRST_SD_H 122 353 #define SRST_NANDC_H 123 354 #define SRST_NANDC_N 124 355 #define SRST_MAC_A 125 356 #define SRST_CAN_P 126 357 #define SRST_OWIRE_P 127 358 359 /* cru_softrst_con8 */ 360 #define SRST_AUDIO_NIU_H 128 361 #define SRST_AUDIO_NIU_P 129 362 #define SRST_PDM_H 130 363 #define SRST_PDM_M 131 364 #define SRST_SPDIFTX_H 132 365 #define SRST_SPDIFTX_M 133 366 #define SRST_SPDIFRX_H 134 367 #define SRST_SPDIFRX_M 135 368 #define SRST_I2S0_8CH_H 136 369 #define SRST_I2S0_8CH_TX_M 137 370 #define SRST_I2S0_8CH_RX_M 138 371 #define SRST_I2S1_8CH_H 139 372 #define SRST_I2S1_8CH_TX_M 140 373 #define SRST_I2S1_8CH_RX_M 141 374 #define SRST_I2S2_8CH_H 142 375 #define SRST_I2S2_8CH_TX_M 143 376 377 /* cru_softrst_con9 */ 378 #define SRST_I2S2_8CH_RX_M 144 379 #define SRST_I2S3_8CH_H 145 380 #define SRST_I2S3_8CH_TX_M 146 381 #define SRST_I2S3_8CH_RX_M 147 382 #define SRST_I2S0_2CH_H 148 383 #define SRST_I2S0_2CH_M 149 384 #define SRST_I2S1_2CH_H 150 385 #define SRST_I2S1_2CH_M 151 386 #define SRST_VAD_H 152 387 #define SRST_ACODEC_P 153 388 389 #endif 390
Indexes created Mon Sep 29 15:09:53 GMT 2025