1 /* $NetBSD: rk3368-cru.h,v 1.1.1.5 2021/11/07 16:49:58 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright (c) 2015 Heiko Stuebner <heiko (at) sntech.de> 6 */ 7 8 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 9 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3368_H 10 11 /* core clocks */ 12 #define PLL_APLLB 1 13 #define PLL_APLLL 2 14 #define PLL_DPLL 3 15 #define PLL_CPLL 4 16 #define PLL_GPLL 5 17 #define PLL_NPLL 6 18 #define ARMCLKB 7 19 #define ARMCLKL 8 20 21 /* sclk gates (special clocks) */ 22 #define SCLK_GPU_CORE 64 23 #define SCLK_SPI0 65 24 #define SCLK_SPI1 66 25 #define SCLK_SPI2 67 26 #define SCLK_SDMMC 68 27 #define SCLK_SDIO0 69 28 #define SCLK_EMMC 71 29 #define SCLK_TSADC 72 30 #define SCLK_SARADC 73 31 #define SCLK_NANDC0 75 32 #define SCLK_UART0 77 33 #define SCLK_UART1 78 34 #define SCLK_UART2 79 35 #define SCLK_UART3 80 36 #define SCLK_UART4 81 37 #define SCLK_I2S_8CH 82 38 #define SCLK_SPDIF_8CH 83 39 #define SCLK_I2S_2CH 84 40 #define SCLK_TIMER00 85 41 #define SCLK_TIMER01 86 42 #define SCLK_TIMER02 87 43 #define SCLK_TIMER03 88 44 #define SCLK_TIMER04 89 45 #define SCLK_TIMER05 90 46 #define SCLK_OTGPHY0 93 47 #define SCLK_OTG_ADP 96 48 #define SCLK_HSICPHY480M 97 49 #define SCLK_HSICPHY12M 98 50 #define SCLK_MACREF 99 51 #define SCLK_VOP0_PWM 100 52 #define SCLK_MAC_RX 102 53 #define SCLK_MAC_TX 103 54 #define SCLK_EDP_24M 104 55 #define SCLK_EDP 105 56 #define SCLK_RGA 106 57 #define SCLK_ISP 107 58 #define SCLK_HDCP 108 59 #define SCLK_HDMI_HDCP 109 60 #define SCLK_HDMI_CEC 110 61 #define SCLK_HEVC_CABAC 111 62 #define SCLK_HEVC_CORE 112 63 #define SCLK_I2S_8CH_OUT 113 64 #define SCLK_SDMMC_DRV 114 65 #define SCLK_SDIO0_DRV 115 66 #define SCLK_EMMC_DRV 117 67 #define SCLK_SDMMC_SAMPLE 118 68 #define SCLK_SDIO0_SAMPLE 119 69 #define SCLK_EMMC_SAMPLE 121 70 #define SCLK_USBPHY480M 122 71 #define SCLK_PVTM_CORE 123 72 #define SCLK_PVTM_GPU 124 73 #define SCLK_PVTM_PMU 125 74 #define SCLK_SFC 126 75 #define SCLK_MAC 127 76 #define SCLK_MACREF_OUT 128 77 #define SCLK_TIMER10 133 78 #define SCLK_TIMER11 134 79 #define SCLK_TIMER12 135 80 #define SCLK_TIMER13 136 81 #define SCLK_TIMER14 137 82 #define SCLK_TIMER15 138 83 #define SCLK_VIP_OUT 139 84 85 #define DCLK_VOP 190 86 #define MCLK_CRYPTO 191 87 88 /* aclk gates */ 89 #define ACLK_GPU_MEM 192 90 #define ACLK_GPU_CFG 193 91 #define ACLK_DMAC_BUS 194 92 #define ACLK_DMAC_PERI 195 93 #define ACLK_PERI_MMU 196 94 #define ACLK_GMAC 197 95 #define ACLK_VOP 198 96 #define ACLK_VOP_IEP 199 97 #define ACLK_RGA 200 98 #define ACLK_HDCP 201 99 #define ACLK_IEP 202 100 #define ACLK_VIO0_NOC 203 101 #define ACLK_VIP 204 102 #define ACLK_ISP 205 103 #define ACLK_VIO1_NOC 206 104 #define ACLK_VIDEO 208 105 #define ACLK_BUS 209 106 #define ACLK_PERI 210 107 108 /* pclk gates */ 109 #define PCLK_GPIO0 320 110 #define PCLK_GPIO1 321 111 #define PCLK_GPIO2 322 112 #define PCLK_GPIO3 323 113 #define PCLK_PMUGRF 324 114 #define PCLK_MAILBOX 325 115 #define PCLK_GRF 329 116 #define PCLK_SGRF 330 117 #define PCLK_PMU 331 118 #define PCLK_I2C0 332 119 #define PCLK_I2C1 333 120 #define PCLK_I2C2 334 121 #define PCLK_I2C3 335 122 #define PCLK_I2C4 336 123 #define PCLK_I2C5 337 124 #define PCLK_SPI0 338 125 #define PCLK_SPI1 339 126 #define PCLK_SPI2 340 127 #define PCLK_UART0 341 128 #define PCLK_UART1 342 129 #define PCLK_UART2 343 130 #define PCLK_UART3 344 131 #define PCLK_UART4 345 132 #define PCLK_TSADC 346 133 #define PCLK_SARADC 347 134 #define PCLK_SIM 348 135 #define PCLK_GMAC 349 136 #define PCLK_PWM0 350 137 #define PCLK_PWM1 351 138 #define PCLK_TIMER0 353 139 #define PCLK_TIMER1 354 140 #define PCLK_EDP_CTRL 355 141 #define PCLK_MIPI_DSI0 356 142 #define PCLK_MIPI_CSI 358 143 #define PCLK_HDCP 359 144 #define PCLK_HDMI_CTRL 360 145 #define PCLK_VIO_H2P 361 146 #define PCLK_BUS 362 147 #define PCLK_PERI 363 148 #define PCLK_DDRUPCTL 364 149 #define PCLK_DDRPHY 365 150 #define PCLK_ISP 366 151 #define PCLK_VIP 367 152 #define PCLK_WDT 368 153 #define PCLK_EFUSE256 369 154 #define PCLK_DPHYRX 370 155 #define PCLK_DPHYTX0 371 156 157 /* hclk gates */ 158 #define HCLK_SFC 448 159 #define HCLK_OTG0 449 160 #define HCLK_HOST0 450 161 #define HCLK_HOST1 451 162 #define HCLK_HSIC 452 163 #define HCLK_NANDC0 453 164 #define HCLK_TSP 455 165 #define HCLK_SDMMC 456 166 #define HCLK_SDIO0 457 167 #define HCLK_EMMC 459 168 #define HCLK_HSADC 460 169 #define HCLK_CRYPTO 461 170 #define HCLK_I2S_2CH 462 171 #define HCLK_I2S_8CH 463 172 #define HCLK_SPDIF 464 173 #define HCLK_VOP 465 174 #define HCLK_ROM 467 175 #define HCLK_IEP 468 176 #define HCLK_ISP 469 177 #define HCLK_RGA 470 178 #define HCLK_VIO_AHB_ARBI 471 179 #define HCLK_VIO_NOC 472 180 #define HCLK_VIP 473 181 #define HCLK_VIO_H2P 474 182 #define HCLK_VIO_HDCPMMU 475 183 #define HCLK_VIDEO 476 184 #define HCLK_BUS 477 185 #define HCLK_PERI 478 186 187 #define CLK_NR_CLKS (HCLK_PERI + 1) 188 189 /* soft-reset indices */ 190 #define SRST_CORE_B0 0 191 #define SRST_CORE_B1 1 192 #define SRST_CORE_B2 2 193 #define SRST_CORE_B3 3 194 #define SRST_CORE_B0_PO 4 195 #define SRST_CORE_B1_PO 5 196 #define SRST_CORE_B2_PO 6 197 #define SRST_CORE_B3_PO 7 198 #define SRST_L2_B 8 199 #define SRST_ADB_B 9 200 #define SRST_PD_CORE_B_NIU 10 201 #define SRST_PDBUS_STRSYS 11 202 #define SRST_SOCDBG_B 14 203 #define SRST_CORE_B_DBG 15 204 205 #define SRST_DMAC1 18 206 #define SRST_INTMEM 19 207 #define SRST_ROM 20 208 #define SRST_SPDIF8CH 21 209 #define SRST_I2S8CH 23 210 #define SRST_MAILBOX 24 211 #define SRST_I2S2CH 25 212 #define SRST_EFUSE_256 26 213 #define SRST_MCU_SYS 28 214 #define SRST_MCU_PO 29 215 #define SRST_MCU_NOC 30 216 #define SRST_EFUSE 31 217 218 #define SRST_GPIO0 32 219 #define SRST_GPIO1 33 220 #define SRST_GPIO2 34 221 #define SRST_GPIO3 35 222 #define SRST_GPIO4 36 223 #define SRST_PMUGRF 41 224 #define SRST_I2C0 42 225 #define SRST_I2C1 43 226 #define SRST_I2C2 44 227 #define SRST_I2C3 45 228 #define SRST_I2C4 46 229 #define SRST_I2C5 47 230 231 #define SRST_DWPWM 48 232 #define SRST_MMC_PERI 49 233 #define SRST_PERIPH_MMU 50 234 #define SRST_GRF 55 235 #define SRST_PMU 56 236 #define SRST_PERIPH_AXI 57 237 #define SRST_PERIPH_AHB 58 238 #define SRST_PERIPH_APB 59 239 #define SRST_PERIPH_NIU 60 240 #define SRST_PDPERI_AHB_ARBI 61 241 #define SRST_EMEM 62 242 #define SRST_USB_PERI 63 243 244 #define SRST_DMAC2 64 245 #define SRST_MAC 66 246 #define SRST_GPS 67 247 #define SRST_RKPWM 69 248 #define SRST_USBHOST0 72 249 #define SRST_HSIC 73 250 #define SRST_HSIC_AUX 74 251 #define SRST_HSIC_PHY 75 252 #define SRST_HSADC 76 253 #define SRST_NANDC0 77 254 #define SRST_SFC 79 255 256 #define SRST_SPI0 83 257 #define SRST_SPI1 84 258 #define SRST_SPI2 85 259 #define SRST_SARADC 87 260 #define SRST_PDALIVE_NIU 88 261 #define SRST_PDPMU_INTMEM 89 262 #define SRST_PDPMU_NIU 90 263 #define SRST_SGRF 91 264 265 #define SRST_VIO_ARBI 96 266 #define SRST_RGA_NIU 97 267 #define SRST_VIO0_NIU_AXI 98 268 #define SRST_VIO_NIU_AHB 99 269 #define SRST_LCDC0_AXI 100 270 #define SRST_LCDC0_AHB 101 271 #define SRST_LCDC0_DCLK 102 272 #define SRST_VIP 104 273 #define SRST_RGA_CORE 105 274 #define SRST_IEP_AXI 106 275 #define SRST_IEP_AHB 107 276 #define SRST_RGA_AXI 108 277 #define SRST_RGA_AHB 109 278 #define SRST_ISP 110 279 #define SRST_EDP_24M 111 280 281 #define SRST_VIDEO_AXI 112 282 #define SRST_VIDEO_AHB 113 283 #define SRST_MIPIDPHYTX 114 284 #define SRST_MIPIDSI0 115 285 #define SRST_MIPIDPHYRX 116 286 #define SRST_MIPICSI 117 287 #define SRST_GPU 120 288 #define SRST_HDMI 121 289 #define SRST_EDP 122 290 #define SRST_PMU_PVTM 123 291 #define SRST_CORE_PVTM 124 292 #define SRST_GPU_PVTM 125 293 #define SRST_GPU_SYS 126 294 #define SRST_GPU_MEM_NIU 127 295 296 #define SRST_MMC0 128 297 #define SRST_SDIO0 129 298 #define SRST_EMMC 131 299 #define SRST_USBOTG_AHB 132 300 #define SRST_USBOTG_PHY 133 301 #define SRST_USBOTG_CON 134 302 #define SRST_USBHOST0_AHB 135 303 #define SRST_USBHOST0_PHY 136 304 #define SRST_USBHOST0_CON 137 305 #define SRST_USBOTG_UTMI 138 306 #define SRST_USBHOST1_UTMI 139 307 #define SRST_USB_ADP 141 308 309 #define SRST_CORESIGHT 144 310 #define SRST_PD_CORE_AHB_NOC 145 311 #define SRST_PD_CORE_APB_NOC 146 312 #define SRST_GIC 148 313 #define SRST_LCDC_PWM0 149 314 #define SRST_RGA_H2P_BRG 153 315 #define SRST_VIDEO 154 316 #define SRST_GPU_CFG_NIU 157 317 #define SRST_TSADC 159 318 319 #define SRST_DDRPHY0 160 320 #define SRST_DDRPHY0_APB 161 321 #define SRST_DDRCTRL0 162 322 #define SRST_DDRCTRL0_APB 163 323 #define SRST_VIDEO_NIU 165 324 #define SRST_VIDEO_NIU_AHB 167 325 #define SRST_DDRMSCH0 170 326 #define SRST_PDBUS_AHB 173 327 #define SRST_CRYPTO 174 328 329 #define SRST_UART0 179 330 #define SRST_UART1 180 331 #define SRST_UART2 181 332 #define SRST_UART3 182 333 #define SRST_UART4 183 334 #define SRST_SIMC 186 335 #define SRST_TSP 188 336 #define SRST_TSP_CLKIN0 189 337 338 #define SRST_CORE_L0 192 339 #define SRST_CORE_L1 193 340 #define SRST_CORE_L2 194 341 #define SRST_CORE_L3 195 342 #define SRST_CORE_L0_PO 195 343 #define SRST_CORE_L1_PO 197 344 #define SRST_CORE_L2_PO 198 345 #define SRST_CORE_L3_PO 199 346 #define SRST_L2_L 200 347 #define SRST_ADB_L 201 348 #define SRST_PD_CORE_L_NIU 202 349 #define SRST_CCI_SYS 203 350 #define SRST_CCI_DDR 204 351 #define SRST_CCI 205 352 #define SRST_SOCDBG_L 206 353 #define SRST_CORE_L_DBG 207 354 355 #define SRST_CORE_B0_NC 208 356 #define SRST_CORE_B0_PO_NC 209 357 #define SRST_L2_B_NC 210 358 #define SRST_ADB_B_NC 211 359 #define SRST_PD_CORE_B_NIU_NC 212 360 #define SRST_PDBUS_STRSYS_NC 213 361 #define SRST_CORE_L0_NC 214 362 #define SRST_CORE_L0_PO_NC 215 363 #define SRST_L2_L_NC 216 364 #define SRST_ADB_L_NC 217 365 #define SRST_PD_CORE_L_NIU_NC 218 366 #define SRST_CCI_SYS_NC 219 367 #define SRST_CCI_DDR_NC 220 368 #define SRST_CCI_NC 221 369 #define SRST_TRACE_NC 222 370 371 #define SRST_TIMER00 224 372 #define SRST_TIMER01 225 373 #define SRST_TIMER02 226 374 #define SRST_TIMER03 227 375 #define SRST_TIMER04 228 376 #define SRST_TIMER05 229 377 #define SRST_TIMER10 230 378 #define SRST_TIMER11 231 379 #define SRST_TIMER12 232 380 #define SRST_TIMER13 233 381 #define SRST_TIMER14 234 382 #define SRST_TIMER15 235 383 #define SRST_TIMER0_APB 236 384 #define SRST_TIMER1_APB 237 385 386 #endif 387
Indexes created Mon Sep 29 21:09:56 GMT 2025