1/* $NetBSD: rockchip,rk3588-cru.h,v 1.1.1.1 2026/01/18 05:21:40 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 4/* 5 * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 6 * Copyright (c) 2022 Collabora Ltd. 7 * 8 * Author: Elaine Zhang <zhangqing@rock-chips.com> 9 * Author: Sebastian Reichel <sebastian.reichel@collabora.com> 10 */ 11 12#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H 13#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H 14 15/* cru-clocks indices */ 16 17#define PLL_B0PLL 0 18#define PLL_B1PLL 1 19#define PLL_LPLL 2 20#define PLL_V0PLL 3 21#define PLL_AUPLL 4 22#define PLL_CPLL 5 23#define PLL_GPLL 6 24#define PLL_NPLL 7 25#define PLL_PPLL 8 26#define ARMCLK_L 9 27#define ARMCLK_B01 10 28#define ARMCLK_B23 11 29#define PCLK_BIGCORE0_ROOT 12 30#define PCLK_BIGCORE0_PVTM 13 31#define PCLK_BIGCORE1_ROOT 14 32#define PCLK_BIGCORE1_PVTM 15 33#define PCLK_DSU_S_ROOT 16 34#define PCLK_DSU_ROOT 17 35#define PCLK_DSU_NS_ROOT 18 36#define PCLK_LITCORE_PVTM 19 37#define PCLK_DBG 20 38#define PCLK_DSU 21 39#define PCLK_S_DAPLITE 22 40#define PCLK_M_DAPLITE 23 41#define MBIST_MCLK_PDM1 24 42#define MBIST_CLK_ACDCDIG 25 43#define HCLK_I2S2_2CH 26 44#define HCLK_I2S3_2CH 27 45#define CLK_I2S2_2CH_SRC 28 46#define CLK_I2S2_2CH_FRAC 29 47#define CLK_I2S2_2CH 30 48#define MCLK_I2S2_2CH 31 49#define I2S2_2CH_MCLKOUT 32 50#define CLK_DAC_ACDCDIG 33 51#define CLK_I2S3_2CH_SRC 34 52#define CLK_I2S3_2CH_FRAC 35 53#define CLK_I2S3_2CH 36 54#define MCLK_I2S3_2CH 37 55#define I2S3_2CH_MCLKOUT 38 56#define PCLK_ACDCDIG 39 57#define HCLK_I2S0_8CH 40 58#define CLK_I2S0_8CH_TX_SRC 41 59#define CLK_I2S0_8CH_TX_FRAC 42 60#define MCLK_I2S0_8CH_TX 43 61#define CLK_I2S0_8CH_TX 44 62#define CLK_I2S0_8CH_RX_SRC 45 63#define CLK_I2S0_8CH_RX_FRAC 46 64#define MCLK_I2S0_8CH_RX 47 65#define CLK_I2S0_8CH_RX 48 66#define I2S0_8CH_MCLKOUT 49 67#define HCLK_PDM1 50 68#define MCLK_PDM1 51 69#define HCLK_AUDIO_ROOT 52 70#define PCLK_AUDIO_ROOT 53 71#define HCLK_SPDIF0 54 72#define CLK_SPDIF0_SRC 55 73#define CLK_SPDIF0_FRAC 56 74#define MCLK_SPDIF0 57 75#define CLK_SPDIF0 58 76#define CLK_SPDIF1 59 77#define HCLK_SPDIF1 60 78#define CLK_SPDIF1_SRC 61 79#define CLK_SPDIF1_FRAC 62 80#define MCLK_SPDIF1 63 81#define ACLK_AV1_ROOT 64 82#define ACLK_AV1 65 83#define PCLK_AV1_ROOT 66 84#define PCLK_AV1 67 85#define PCLK_MAILBOX0 68 86#define PCLK_MAILBOX1 69 87#define PCLK_MAILBOX2 70 88#define PCLK_PMU2 71 89#define PCLK_PMUCM0_INTMUX 72 90#define PCLK_DDRCM0_INTMUX 73 91#define PCLK_TOP 74 92#define PCLK_PWM1 75 93#define CLK_PWM1 76 94#define CLK_PWM1_CAPTURE 77 95#define PCLK_PWM2 78 96#define CLK_PWM2 79 97#define CLK_PWM2_CAPTURE 80 98#define PCLK_PWM3 81 99#define CLK_PWM3 82 100#define CLK_PWM3_CAPTURE 83 101#define PCLK_BUSTIMER0 84 102#define PCLK_BUSTIMER1 85 103#define CLK_BUS_TIMER_ROOT 86 104#define CLK_BUSTIMER0 87 105#define CLK_BUSTIMER1 88 106#define CLK_BUSTIMER2 89 107#define CLK_BUSTIMER3 90 108#define CLK_BUSTIMER4 91 109#define CLK_BUSTIMER5 92 110#define CLK_BUSTIMER6 93 111#define CLK_BUSTIMER7 94 112#define CLK_BUSTIMER8 95 113#define CLK_BUSTIMER9 96 114#define CLK_BUSTIMER10 97 115#define CLK_BUSTIMER11 98 116#define PCLK_WDT0 99 117#define TCLK_WDT0 100 118#define PCLK_CAN0 101 119#define CLK_CAN0 102 120#define PCLK_CAN1 103 121#define CLK_CAN1 104 122#define PCLK_CAN2 105 123#define CLK_CAN2 106 124#define ACLK_DECOM 107 125#define PCLK_DECOM 108 126#define DCLK_DECOM 109 127#define ACLK_DMAC0 110 128#define ACLK_DMAC1 111 129#define ACLK_DMAC2 112 130#define ACLK_BUS_ROOT 113 131#define ACLK_GIC 114 132#define PCLK_GPIO1 115 133#define DBCLK_GPIO1 116 134#define PCLK_GPIO2 117 135#define DBCLK_GPIO2 118 136#define PCLK_GPIO3 119 137#define DBCLK_GPIO3 120 138#define PCLK_GPIO4 121 139#define DBCLK_GPIO4 122 140#define PCLK_I2C1 123 141#define PCLK_I2C2 124 142#define PCLK_I2C3 125 143#define PCLK_I2C4 126 144#define PCLK_I2C5 127 145#define PCLK_I2C6 128 146#define PCLK_I2C7 129 147#define PCLK_I2C8 130 148#define CLK_I2C1 131 149#define CLK_I2C2 132 150#define CLK_I2C3 133 151#define CLK_I2C4 134 152#define CLK_I2C5 135 153#define CLK_I2C6 136 154#define CLK_I2C7 137 155#define CLK_I2C8 138 156#define PCLK_OTPC_NS 139 157#define CLK_OTPC_NS 140 158#define CLK_OTPC_ARB 141 159#define CLK_OTPC_AUTO_RD_G 142 160#define CLK_OTP_PHY_G 143 161#define PCLK_SARADC 144 162#define CLK_SARADC 145 163#define PCLK_SPI0 146 164#define PCLK_SPI1 147 165#define PCLK_SPI2 148 166#define PCLK_SPI3 149 167#define PCLK_SPI4 150 168#define CLK_SPI0 151 169#define CLK_SPI1 152 170#define CLK_SPI2 153 171#define CLK_SPI3 154 172#define CLK_SPI4 155 173#define ACLK_SPINLOCK 156 174#define PCLK_TSADC 157 175#define CLK_TSADC 158 176#define PCLK_UART1 159 177#define PCLK_UART2 160 178#define PCLK_UART3 161 179#define PCLK_UART4 162 180#define PCLK_UART5 163 181#define PCLK_UART6 164 182#define PCLK_UART7 165 183#define PCLK_UART8 166 184#define PCLK_UART9 167 185#define CLK_UART1_SRC 168 186#define CLK_UART1_FRAC 169 187#define CLK_UART1 170 188#define SCLK_UART1 171 189#define CLK_UART2_SRC 172 190#define CLK_UART2_FRAC 173 191#define CLK_UART2 174 192#define SCLK_UART2 175 193#define CLK_UART3_SRC 176 194#define CLK_UART3_FRAC 177 195#define CLK_UART3 178 196#define SCLK_UART3 179 197#define CLK_UART4_SRC 180 198#define CLK_UART4_FRAC 181 199#define CLK_UART4 182 200#define SCLK_UART4 183 201#define CLK_UART5_SRC 184 202#define CLK_UART5_FRAC 185 203#define CLK_UART5 186 204#define SCLK_UART5 187 205#define CLK_UART6_SRC 188 206#define CLK_UART6_FRAC 189 207#define CLK_UART6 190 208#define SCLK_UART6 191 209#define CLK_UART7_SRC 192 210#define CLK_UART7_FRAC 193 211#define CLK_UART7 194 212#define SCLK_UART7 195 213#define CLK_UART8_SRC 196 214#define CLK_UART8_FRAC 197 215#define CLK_UART8 198 216#define SCLK_UART8 199 217#define CLK_UART9_SRC 200 218#define CLK_UART9_FRAC 201 219#define CLK_UART9 202 220#define SCLK_UART9 203 221#define ACLK_CENTER_ROOT 204 222#define ACLK_CENTER_LOW_ROOT 205 223#define HCLK_CENTER_ROOT 206 224#define PCLK_CENTER_ROOT 207 225#define ACLK_DMA2DDR 208 226#define ACLK_DDR_SHAREMEM 209 227#define ACLK_CENTER_S200_ROOT 210 228#define ACLK_CENTER_S400_ROOT 211 229#define FCLK_DDR_CM0_CORE 212 230#define CLK_DDR_TIMER_ROOT 213 231#define CLK_DDR_TIMER0 214 232#define CLK_DDR_TIMER1 215 233#define TCLK_WDT_DDR 216 234#define CLK_DDR_CM0_RTC 217 235#define PCLK_WDT 218 236#define PCLK_TIMER 219 237#define PCLK_DMA2DDR 220 238#define PCLK_SHAREMEM 221 239#define CLK_50M_SRC 222 240#define CLK_100M_SRC 223 241#define CLK_150M_SRC 224 242#define CLK_200M_SRC 225 243#define CLK_250M_SRC 226 244#define CLK_300M_SRC 227 245#define CLK_350M_SRC 228 246#define CLK_400M_SRC 229 247#define CLK_450M_SRC 230 248#define CLK_500M_SRC 231 249#define CLK_600M_SRC 232 250#define CLK_650M_SRC 233 251#define CLK_700M_SRC 234 252#define CLK_800M_SRC 235 253#define CLK_1000M_SRC 236 254#define CLK_1200M_SRC 237 255#define ACLK_TOP_M300_ROOT 238 256#define ACLK_TOP_M500_ROOT 239 257#define ACLK_TOP_M400_ROOT 240 258#define ACLK_TOP_S200_ROOT 241 259#define ACLK_TOP_S400_ROOT 242 260#define CLK_MIPI_CAMARAOUT_M0 243 261#define CLK_MIPI_CAMARAOUT_M1 244 262#define CLK_MIPI_CAMARAOUT_M2 245 263#define CLK_MIPI_CAMARAOUT_M3 246 264#define CLK_MIPI_CAMARAOUT_M4 247 265#define MCLK_GMAC0_OUT 248 266#define REFCLKO25M_ETH0_OUT 249 267#define REFCLKO25M_ETH1_OUT 250 268#define CLK_CIFOUT_OUT 251 269#define PCLK_MIPI_DCPHY0 252 270#define PCLK_MIPI_DCPHY1 253 271#define PCLK_CSIPHY0 254 272#define PCLK_CSIPHY1 255 273#define ACLK_TOP_ROOT 256 274#define PCLK_TOP_ROOT 257 275#define ACLK_LOW_TOP_ROOT 258 276#define PCLK_CRU 259 277#define PCLK_GPU_ROOT 260 278#define CLK_GPU_SRC 261 279#define CLK_GPU 262 280#define CLK_GPU_COREGROUP 263 281#define CLK_GPU_STACKS 264 282#define PCLK_GPU_PVTM 265 283#define CLK_GPU_PVTM 266 284#define CLK_CORE_GPU_PVTM 267 285#define PCLK_GPU_GRF 268 286#define ACLK_ISP1_ROOT 269 287#define HCLK_ISP1_ROOT 270 288#define CLK_ISP1_CORE 271 289#define CLK_ISP1_CORE_MARVIN 272 290#define CLK_ISP1_CORE_VICAP 273 291#define ACLK_ISP1 274 292#define HCLK_ISP1 275 293#define ACLK_NPU1 276 294#define HCLK_NPU1 277 295#define ACLK_NPU2 278 296#define HCLK_NPU2 279 297#define HCLK_NPU_CM0_ROOT 280 298#define FCLK_NPU_CM0_CORE 281 299#define CLK_NPU_CM0_RTC 282 300#define PCLK_NPU_PVTM 283 301#define PCLK_NPU_GRF 284 302#define CLK_NPU_PVTM 285 303#define CLK_CORE_NPU_PVTM 286 304#define ACLK_NPU0 287 305#define HCLK_NPU0 288 306#define HCLK_NPU_ROOT 289 307#define CLK_NPU_DSU0 290 308#define PCLK_NPU_ROOT 291 309#define PCLK_NPU_TIMER 292 310#define CLK_NPUTIMER_ROOT 293 311#define CLK_NPUTIMER0 294 312#define CLK_NPUTIMER1 295 313#define PCLK_NPU_WDT 296 314#define TCLK_NPU_WDT 297 315#define HCLK_EMMC 298 316#define ACLK_EMMC 299 317#define CCLK_EMMC 300 318#define BCLK_EMMC 301 319#define TMCLK_EMMC 302 320#define SCLK_SFC 303 321#define HCLK_SFC 304 322#define HCLK_SFC_XIP 305 323#define HCLK_NVM_ROOT 306 324#define ACLK_NVM_ROOT 307 325#define CLK_GMAC0_PTP_REF 308 326#define CLK_GMAC1_PTP_REF 309 327#define CLK_GMAC_125M 310 328#define CLK_GMAC_50M 311 329#define ACLK_PHP_GIC_ITS 312 330#define ACLK_MMU_PCIE 313 331#define ACLK_MMU_PHP 314 332#define ACLK_PCIE_4L_DBI 315 333#define ACLK_PCIE_2L_DBI 316 334#define ACLK_PCIE_1L0_DBI 317 335#define ACLK_PCIE_1L1_DBI 318 336#define ACLK_PCIE_1L2_DBI 319 337#define ACLK_PCIE_4L_MSTR 320 338#define ACLK_PCIE_2L_MSTR 321 339#define ACLK_PCIE_1L0_MSTR 322 340#define ACLK_PCIE_1L1_MSTR 323 341#define ACLK_PCIE_1L2_MSTR 324 342#define ACLK_PCIE_4L_SLV 325 343#define ACLK_PCIE_2L_SLV 326 344#define ACLK_PCIE_1L0_SLV 327 345#define ACLK_PCIE_1L1_SLV 328 346#define ACLK_PCIE_1L2_SLV 329 347#define PCLK_PCIE_4L 330 348#define PCLK_PCIE_2L 331 349#define PCLK_PCIE_1L0 332 350#define PCLK_PCIE_1L1 333 351#define PCLK_PCIE_1L2 334 352#define CLK_PCIE_AUX0 335 353#define CLK_PCIE_AUX1 336 354#define CLK_PCIE_AUX2 337 355#define CLK_PCIE_AUX3 338 356#define CLK_PCIE_AUX4 339 357#define CLK_PIPEPHY0_REF 340 358#define CLK_PIPEPHY1_REF 341 359#define CLK_PIPEPHY2_REF 342 360#define PCLK_PHP_ROOT 343 361#define PCLK_GMAC0 344 362#define PCLK_GMAC1 345 363#define ACLK_PCIE_ROOT 346 364#define ACLK_PHP_ROOT 347 365#define ACLK_PCIE_BRIDGE 348 366#define ACLK_GMAC0 349 367#define ACLK_GMAC1 350 368#define CLK_PMALIVE0 351 369#define CLK_PMALIVE1 352 370#define CLK_PMALIVE2 353 371#define ACLK_SATA0 354 372#define ACLK_SATA1 355 373#define ACLK_SATA2 356 374#define CLK_RXOOB0 357 375#define CLK_RXOOB1 358 376#define CLK_RXOOB2 359 377#define ACLK_USB3OTG2 360 378#define SUSPEND_CLK_USB3OTG2 361 379#define REF_CLK_USB3OTG2 362 380#define CLK_UTMI_OTG2 363 381#define CLK_PIPEPHY0_PIPE_G 364 382#define CLK_PIPEPHY1_PIPE_G 365 383#define CLK_PIPEPHY2_PIPE_G 366 384#define CLK_PIPEPHY0_PIPE_ASIC_G 367 385#define CLK_PIPEPHY1_PIPE_ASIC_G 368 386#define CLK_PIPEPHY2_PIPE_ASIC_G 369 387#define CLK_PIPEPHY2_PIPE_U3_G 370 388#define CLK_PCIE1L2_PIPE 371 389#define CLK_PCIE4L_PIPE 372 390#define CLK_PCIE2L_PIPE 373 391#define PCLK_PCIE_COMBO_PIPE_PHY0 374 392#define PCLK_PCIE_COMBO_PIPE_PHY1 375 393#define PCLK_PCIE_COMBO_PIPE_PHY2 376 394#define PCLK_PCIE_COMBO_PIPE_PHY 377 395#define HCLK_RGA3_1 378 396#define ACLK_RGA3_1 379 397#define CLK_RGA3_1_CORE 380 398#define ACLK_RGA3_ROOT 381 399#define HCLK_RGA3_ROOT 382 400#define ACLK_RKVDEC_CCU 383 401#define HCLK_RKVDEC0 384 402#define ACLK_RKVDEC0 385 403#define CLK_RKVDEC0_CA 386 404#define CLK_RKVDEC0_HEVC_CA 387 405#define CLK_RKVDEC0_CORE 388 406#define HCLK_RKVDEC1 389 407#define ACLK_RKVDEC1 390 408#define CLK_RKVDEC1_CA 391 409#define CLK_RKVDEC1_HEVC_CA 392 410#define CLK_RKVDEC1_CORE 393 411#define HCLK_SDIO 394 412#define CCLK_SRC_SDIO 395 413#define ACLK_USB_ROOT 396 414#define HCLK_USB_ROOT 397 415#define HCLK_HOST0 398 416#define HCLK_HOST_ARB0 399 417#define HCLK_HOST1 400 418#define HCLK_HOST_ARB1 401 419#define ACLK_USB3OTG0 402 420#define SUSPEND_CLK_USB3OTG0 403 421#define REF_CLK_USB3OTG0 404 422#define ACLK_USB3OTG1 405 423#define SUSPEND_CLK_USB3OTG1 406 424#define REF_CLK_USB3OTG1 407 425#define UTMI_OHCI_CLK48_HOST0 408 426#define UTMI_OHCI_CLK48_HOST1 409 427#define HCLK_IEP2P0 410 428#define ACLK_IEP2P0 411 429#define CLK_IEP2P0_CORE 412 430#define ACLK_JPEG_ENCODER0 413 431#define HCLK_JPEG_ENCODER0 414 432#define ACLK_JPEG_ENCODER1 415 433#define HCLK_JPEG_ENCODER1 416 434#define ACLK_JPEG_ENCODER2 417 435#define HCLK_JPEG_ENCODER2 418 436#define ACLK_JPEG_ENCODER3 419 437#define HCLK_JPEG_ENCODER3 420 438#define ACLK_JPEG_DECODER 421 439#define HCLK_JPEG_DECODER 422 440#define HCLK_RGA2 423 441#define ACLK_RGA2 424 442#define CLK_RGA2_CORE 425 443#define HCLK_RGA3_0 426 444#define ACLK_RGA3_0 427 445#define CLK_RGA3_0_CORE 428 446#define ACLK_VDPU_ROOT 429 447#define ACLK_VDPU_LOW_ROOT 430 448#define HCLK_VDPU_ROOT 431 449#define ACLK_JPEG_DECODER_ROOT 432 450#define ACLK_VPU 433 451#define HCLK_VPU 434 452#define HCLK_RKVENC0_ROOT 435 453#define ACLK_RKVENC0_ROOT 436 454#define HCLK_RKVENC0 437 455#define ACLK_RKVENC0 438 456#define CLK_RKVENC0_CORE 439 457#define HCLK_RKVENC1_ROOT 440 458#define ACLK_RKVENC1_ROOT 441 459#define HCLK_RKVENC1 442 460#define ACLK_RKVENC1 443 461#define CLK_RKVENC1_CORE 444 462#define ICLK_CSIHOST01 445 463#define ICLK_CSIHOST0 446 464#define ICLK_CSIHOST1 447 465#define PCLK_CSI_HOST_0 448 466#define PCLK_CSI_HOST_1 449 467#define PCLK_CSI_HOST_2 450 468#define PCLK_CSI_HOST_3 451 469#define PCLK_CSI_HOST_4 452 470#define PCLK_CSI_HOST_5 453 471#define ACLK_FISHEYE0 454 472#define HCLK_FISHEYE0 455 473#define CLK_FISHEYE0_CORE 456 474#define ACLK_FISHEYE1 457 475#define HCLK_FISHEYE1 458 476#define CLK_FISHEYE1_CORE 459 477#define CLK_ISP0_CORE 460 478#define CLK_ISP0_CORE_MARVIN 461 479#define CLK_ISP0_CORE_VICAP 462 480#define ACLK_ISP0 463 481#define HCLK_ISP0 464 482#define ACLK_VI_ROOT 465 483#define HCLK_VI_ROOT 466 484#define PCLK_VI_ROOT 467 485#define DCLK_VICAP 468 486#define ACLK_VICAP 469 487#define HCLK_VICAP 470 488#define PCLK_DP0 471 489#define PCLK_DP1 472 490#define PCLK_S_DP0 473 491#define PCLK_S_DP1 474 492#define CLK_DP0 475 493#define CLK_DP1 476 494#define HCLK_HDCP_KEY0 477 495#define ACLK_HDCP0 478 496#define HCLK_HDCP0 479 497#define PCLK_HDCP0 480 498#define HCLK_I2S4_8CH 481 499#define ACLK_TRNG0 482 500#define PCLK_TRNG0 483 501#define ACLK_VO0_ROOT 484 502#define HCLK_VO0_ROOT 485 503#define HCLK_VO0_S_ROOT 486 504#define PCLK_VO0_ROOT 487 505#define PCLK_VO0_S_ROOT 488 506#define PCLK_VO0GRF 489 507#define CLK_I2S4_8CH_TX_SRC 490 508#define CLK_I2S4_8CH_TX_FRAC 491 509#define MCLK_I2S4_8CH_TX 492 510#define CLK_I2S4_8CH_TX 493 511#define HCLK_I2S8_8CH 494 512#define CLK_I2S8_8CH_TX_SRC 495 513#define CLK_I2S8_8CH_TX_FRAC 496 514#define MCLK_I2S8_8CH_TX 497 515#define CLK_I2S8_8CH_TX 498 516#define HCLK_SPDIF2_DP0 499 517#define CLK_SPDIF2_DP0_SRC 500 518#define CLK_SPDIF2_DP0_FRAC 501 519#define MCLK_SPDIF2_DP0 502 520#define CLK_SPDIF2_DP0 503 521#define MCLK_SPDIF2 504 522#define HCLK_SPDIF5_DP1 505 523#define CLK_SPDIF5_DP1_SRC 506 524#define CLK_SPDIF5_DP1_FRAC 507 525#define MCLK_SPDIF5_DP1 508 526#define CLK_SPDIF5_DP1 509 527#define MCLK_SPDIF5 510 528#define PCLK_EDP0 511 529#define CLK_EDP0_24M 512 530#define CLK_EDP0_200M 513 531#define PCLK_EDP1 514 532#define CLK_EDP1_24M 515 533#define CLK_EDP1_200M 516 534#define HCLK_HDCP_KEY1 517 535#define ACLK_HDCP1 518 536#define HCLK_HDCP1 519 537#define PCLK_HDCP1 520 538#define ACLK_HDMIRX 521 539#define PCLK_HDMIRX 522 540#define CLK_HDMIRX_REF 523 541#define CLK_HDMIRX_AUD_SRC 524 542#define CLK_HDMIRX_AUD_FRAC 525 543#define CLK_HDMIRX_AUD 526 544#define CLK_HDMIRX_AUD_P_MUX 527 545#define PCLK_HDMITX0 528 546#define CLK_HDMITX0_EARC 529 547#define CLK_HDMITX0_REF 530 548#define PCLK_HDMITX1 531 549#define CLK_HDMITX1_EARC 532 550#define CLK_HDMITX1_REF 533 551#define CLK_HDMITRX_REFSRC 534 552#define ACLK_TRNG1 535 553#define PCLK_TRNG1 536 554#define ACLK_HDCP1_ROOT 537 555#define ACLK_HDMIRX_ROOT 538 556#define HCLK_VO1_ROOT 539 557#define HCLK_VO1_S_ROOT 540 558#define PCLK_VO1_ROOT 541 559#define PCLK_VO1_S_ROOT 542 560#define PCLK_S_EDP0 543 561#define PCLK_S_EDP1 544 562#define PCLK_S_HDMIRX 545 563#define HCLK_I2S10_8CH 546 564#define CLK_I2S10_8CH_RX_SRC 547 565#define CLK_I2S10_8CH_RX_FRAC 548 566#define CLK_I2S10_8CH_RX 549 567#define MCLK_I2S10_8CH_RX 550 568#define HCLK_I2S7_8CH 551 569#define CLK_I2S7_8CH_RX_SRC 552 570#define CLK_I2S7_8CH_RX_FRAC 553 571#define CLK_I2S7_8CH_RX 554 572#define MCLK_I2S7_8CH_RX 555 573#define HCLK_I2S9_8CH 556 574#define CLK_I2S9_8CH_RX_SRC 557 575#define CLK_I2S9_8CH_RX_FRAC 558 576#define CLK_I2S9_8CH_RX 559 577#define MCLK_I2S9_8CH_RX 560 578#define CLK_I2S5_8CH_TX_SRC 561 579#define CLK_I2S5_8CH_TX_FRAC 562 580#define CLK_I2S5_8CH_TX 563 581#define MCLK_I2S5_8CH_TX 564 582#define HCLK_I2S5_8CH 565 583#define CLK_I2S6_8CH_TX_SRC 566 584#define CLK_I2S6_8CH_TX_FRAC 567 585#define CLK_I2S6_8CH_TX 568 586#define MCLK_I2S6_8CH_TX 569 587#define CLK_I2S6_8CH_RX_SRC 570 588#define CLK_I2S6_8CH_RX_FRAC 571 589#define CLK_I2S6_8CH_RX 572 590#define MCLK_I2S6_8CH_RX 573 591#define I2S6_8CH_MCLKOUT 574 592#define HCLK_I2S6_8CH 575 593#define HCLK_SPDIF3 576 594#define CLK_SPDIF3_SRC 577 595#define CLK_SPDIF3_FRAC 578 596#define CLK_SPDIF3 579 597#define MCLK_SPDIF3 580 598#define HCLK_SPDIF4 581 599#define CLK_SPDIF4_SRC 582 600#define CLK_SPDIF4_FRAC 583 601#define CLK_SPDIF4 584 602#define MCLK_SPDIF4 585 603#define HCLK_SPDIFRX0 586 604#define MCLK_SPDIFRX0 587 605#define HCLK_SPDIFRX1 588 606#define MCLK_SPDIFRX1 589 607#define HCLK_SPDIFRX2 590 608#define MCLK_SPDIFRX2 591 609#define ACLK_VO1USB_TOP_ROOT 592 610#define HCLK_VO1USB_TOP_ROOT 593 611#define CLK_HDMIHDP0 594 612#define CLK_HDMIHDP1 595 613#define PCLK_HDPTX0 596 614#define PCLK_HDPTX1 597 615#define PCLK_USBDPPHY0 598 616#define PCLK_USBDPPHY1 599 617#define ACLK_VOP_ROOT 600 618#define ACLK_VOP_LOW_ROOT 601 619#define HCLK_VOP_ROOT 602 620#define PCLK_VOP_ROOT 603 621#define HCLK_VOP 604 622#define ACLK_VOP 605 623#define DCLK_VOP0_SRC 606 624#define DCLK_VOP1_SRC 607 625#define DCLK_VOP2_SRC 608 626#define DCLK_VOP0 609 627#define DCLK_VOP1 610 628#define DCLK_VOP2 611 629#define DCLK_VOP3 612 630#define PCLK_DSIHOST0 613 631#define PCLK_DSIHOST1 614 632#define CLK_DSIHOST0 615 633#define CLK_DSIHOST1 616 634#define CLK_VOP_PMU 617 635#define ACLK_VOP_DOBY 618 636#define ACLK_VOP_SUB_SRC 619 637#define CLK_USBDP_PHY0_IMMORTAL 620 638#define CLK_USBDP_PHY1_IMMORTAL 621 639#define CLK_PMU0 622 640#define PCLK_PMU0 623 641#define PCLK_PMU0IOC 624 642#define PCLK_GPIO0 625 643#define DBCLK_GPIO0 626 644#define PCLK_I2C0 627 645#define CLK_I2C0 628 646#define HCLK_I2S1_8CH 629 647#define CLK_I2S1_8CH_TX_SRC 630 648#define CLK_I2S1_8CH_TX_FRAC 631 649#define CLK_I2S1_8CH_TX 632 650#define MCLK_I2S1_8CH_TX 633 651#define CLK_I2S1_8CH_RX_SRC 634 652#define CLK_I2S1_8CH_RX_FRAC 635 653#define CLK_I2S1_8CH_RX 636 654#define MCLK_I2S1_8CH_RX 637 655#define I2S1_8CH_MCLKOUT 638 656#define CLK_PMU1_50M_SRC 639 657#define CLK_PMU1_100M_SRC 640 658#define CLK_PMU1_200M_SRC 641 659#define CLK_PMU1_300M_SRC 642 660#define CLK_PMU1_400M_SRC 643 661#define HCLK_PMU1_ROOT 644 662#define PCLK_PMU1_ROOT 645 663#define PCLK_PMU0_ROOT 646 664#define HCLK_PMU_CM0_ROOT 647 665#define PCLK_PMU1 648 666#define CLK_DDR_FAIL_SAFE 649 667#define CLK_PMU1 650 668#define HCLK_PDM0 651 669#define MCLK_PDM0 652 670#define HCLK_VAD 653 671#define FCLK_PMU_CM0_CORE 654 672#define CLK_PMU_CM0_RTC 655 673#define PCLK_PMU1_IOC 656 674#define PCLK_PMU1PWM 657 675#define CLK_PMU1PWM 658 676#define CLK_PMU1PWM_CAPTURE 659 677#define PCLK_PMU1TIMER 660 678#define CLK_PMU1TIMER_ROOT 661 679#define CLK_PMU1TIMER0 662 680#define CLK_PMU1TIMER1 663 681#define CLK_UART0_SRC 664 682#define CLK_UART0_FRAC 665 683#define CLK_UART0 666 684#define SCLK_UART0 667 685#define PCLK_UART0 668 686#define PCLK_PMU1WDT 669 687#define TCLK_PMU1WDT 670 688#define CLK_CR_PARA 671 689#define CLK_USB2PHY_HDPTXRXPHY_REF 672 690#define CLK_USBDPPHY_MIPIDCPPHY_REF 673 691#define CLK_REF_PIPE_PHY0_OSC_SRC 674 692#define CLK_REF_PIPE_PHY1_OSC_SRC 675 693#define CLK_REF_PIPE_PHY2_OSC_SRC 676 694#define CLK_REF_PIPE_PHY0_PLL_SRC 677 695#define CLK_REF_PIPE_PHY1_PLL_SRC 678 696#define CLK_REF_PIPE_PHY2_PLL_SRC 679 697#define CLK_REF_PIPE_PHY0 680 698#define CLK_REF_PIPE_PHY1 681 699#define CLK_REF_PIPE_PHY2 682 700#define SCLK_SDIO_DRV 683 701#define SCLK_SDIO_SAMPLE 684 702#define SCLK_SDMMC_DRV 685 703#define SCLK_SDMMC_SAMPLE 686 704#define CLK_PCIE1L0_PIPE 687 705#define CLK_PCIE1L1_PIPE 688 706#define CLK_BIGCORE0_PVTM 689 707#define CLK_CORE_BIGCORE0_PVTM 690 708#define CLK_BIGCORE1_PVTM 691 709#define CLK_CORE_BIGCORE1_PVTM 692 710#define CLK_LITCORE_PVTM 693 711#define CLK_CORE_LITCORE_PVTM 694 712#define CLK_AUX16M_0 695 713#define CLK_AUX16M_1 696 714#define CLK_PHY0_REF_ALT_P 697 715#define CLK_PHY0_REF_ALT_M 698 716#define CLK_PHY1_REF_ALT_P 699 717#define CLK_PHY1_REF_ALT_M 700 718#define ACLK_ISP1_PRE 701 719#define HCLK_ISP1_PRE 702 720#define HCLK_NVM 703 721#define ACLK_USB 704 722#define HCLK_USB 705 723#define ACLK_JPEG_DECODER_PRE 706 724#define ACLK_VDPU_LOW_PRE 707 725#define ACLK_RKVENC1_PRE 708 726#define HCLK_RKVENC1_PRE 709 727#define HCLK_RKVDEC0_PRE 710 728#define ACLK_RKVDEC0_PRE 711 729#define HCLK_RKVDEC1_PRE 712 730#define ACLK_RKVDEC1_PRE 713 731#define ACLK_HDCP0_PRE 714 732#define HCLK_VO0 715 733#define ACLK_HDCP1_PRE 716 734#define HCLK_VO1 717 735#define ACLK_AV1_PRE 718 736#define PCLK_AV1_PRE 719 737#define HCLK_SDIO_PRE 720 738#define PCLK_VO1GRF 721 739 740/* scmi-clocks indices */ 741 742#define SCMI_CLK_CPUL 0 743#define SCMI_CLK_DSU 1 744#define SCMI_CLK_CPUB01 2 745#define SCMI_CLK_CPUB23 3 746#define SCMI_CLK_DDR 4 747#define SCMI_CLK_GPU 5 748#define SCMI_CLK_NPU 6 749#define SCMI_CLK_SBUS 7 750#define SCMI_PCLK_SBUS 8 751#define SCMI_CCLK_SD 9 752#define SCMI_DCLK_SD 10 753#define SCMI_ACLK_SECURE_NS 11 754#define SCMI_HCLK_SECURE_NS 12 755#define SCMI_TCLK_WDT 13 756#define SCMI_KEYLADDER_CORE 14 757#define SCMI_KEYLADDER_RNG 15 758#define SCMI_ACLK_SECURE_S 16 759#define SCMI_HCLK_SECURE_S 17 760#define SCMI_PCLK_SECURE_S 18 761#define SCMI_CRYPTO_RNG 19 762#define SCMI_CRYPTO_CORE 20 763#define SCMI_CRYPTO_PKA 21 764#define SCMI_SPLL 22 765#define SCMI_HCLK_SD 23 766 767#endif 768