1 /* $NetBSD: rockchip,rk3576-cru.h,v 1.1.1.1 2026/01/18 05:21:40 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 4 /* 5 * Copyright (c) 2023 Rockchip Electronics Co. Ltd. 6 * Copyright (c) 2024 Collabora Ltd. 7 * 8 * Author: Elaine Zhang <zhangqing (at) rock-chips.com> 9 * Author: Detlev Casanova <detlev.casanova (at) collabora.com> 10 */ 11 12 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H 13 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H 14 15 /* cru-clocks indices */ 16 17 /* cru plls */ 18 #define PLL_BPLL 0 19 #define PLL_LPLL 1 20 #define PLL_VPLL 2 21 #define PLL_AUPLL 3 22 #define PLL_CPLL 4 23 #define PLL_GPLL 5 24 #define PLL_PPLL 6 25 #define ARMCLK_L 7 26 #define ARMCLK_B 8 27 28 /* cru clocks */ 29 #define CLK_CPLL_DIV20 9 30 #define CLK_CPLL_DIV10 10 31 #define CLK_GPLL_DIV8 11 32 #define CLK_GPLL_DIV6 12 33 #define CLK_CPLL_DIV4 13 34 #define CLK_GPLL_DIV4 14 35 #define CLK_SPLL_DIV2 15 36 #define CLK_GPLL_DIV3 16 37 #define CLK_CPLL_DIV2 17 38 #define CLK_GPLL_DIV2 18 39 #define CLK_SPLL_DIV1 19 40 #define PCLK_TOP_ROOT 20 41 #define ACLK_TOP 21 42 #define HCLK_TOP 22 43 #define CLK_AUDIO_FRAC_0 23 44 #define CLK_AUDIO_FRAC_1 24 45 #define CLK_AUDIO_FRAC_2 25 46 #define CLK_AUDIO_FRAC_3 26 47 #define CLK_UART_FRAC_0 27 48 #define CLK_UART_FRAC_1 28 49 #define CLK_UART_FRAC_2 29 50 #define CLK_UART1_SRC_TOP 30 51 #define CLK_AUDIO_INT_0 31 52 #define CLK_AUDIO_INT_1 32 53 #define CLK_AUDIO_INT_2 33 54 #define CLK_PDM0_SRC_TOP 34 55 #define CLK_PDM1_OUT 35 56 #define CLK_GMAC0_125M_SRC 36 57 #define CLK_GMAC1_125M_SRC 37 58 #define LCLK_ASRC_SRC_0 38 59 #define LCLK_ASRC_SRC_1 39 60 #define REF_CLK0_OUT_PLL 40 61 #define REF_CLK1_OUT_PLL 41 62 #define REF_CLK2_OUT_PLL 42 63 #define REFCLKO25M_GMAC0_OUT 43 64 #define REFCLKO25M_GMAC1_OUT 44 65 #define CLK_CIFOUT_OUT 45 66 #define CLK_GMAC0_RMII_CRU 46 67 #define CLK_GMAC1_RMII_CRU 47 68 #define CLK_OTPC_AUTO_RD_G 48 69 #define CLK_OTP_PHY_G 49 70 #define CLK_MIPI_CAMERAOUT_M0 50 71 #define CLK_MIPI_CAMERAOUT_M1 51 72 #define CLK_MIPI_CAMERAOUT_M2 52 73 #define MCLK_PDM0_SRC_TOP 53 74 #define HCLK_AUDIO_ROOT 54 75 #define HCLK_ASRC_2CH_0 55 76 #define HCLK_ASRC_2CH_1 56 77 #define HCLK_ASRC_4CH_0 57 78 #define HCLK_ASRC_4CH_1 58 79 #define CLK_ASRC_2CH_0 59 80 #define CLK_ASRC_2CH_1 60 81 #define CLK_ASRC_4CH_0 61 82 #define CLK_ASRC_4CH_1 62 83 #define MCLK_SAI0_8CH_SRC 63 84 #define MCLK_SAI0_8CH 64 85 #define HCLK_SAI0_8CH 65 86 #define HCLK_SPDIF_RX0 66 87 #define MCLK_SPDIF_RX0 67 88 #define HCLK_SPDIF_RX1 68 89 #define MCLK_SPDIF_RX1 69 90 #define MCLK_SAI1_8CH_SRC 70 91 #define MCLK_SAI1_8CH 71 92 #define HCLK_SAI1_8CH 72 93 #define MCLK_SAI2_2CH_SRC 73 94 #define MCLK_SAI2_2CH 74 95 #define HCLK_SAI2_2CH 75 96 #define MCLK_SAI3_2CH_SRC 76 97 #define MCLK_SAI3_2CH 77 98 #define HCLK_SAI3_2CH 78 99 #define MCLK_SAI4_2CH_SRC 79 100 #define MCLK_SAI4_2CH 80 101 #define HCLK_SAI4_2CH 81 102 #define HCLK_ACDCDIG_DSM 82 103 #define MCLK_ACDCDIG_DSM 83 104 #define CLK_PDM1 84 105 #define HCLK_PDM1 85 106 #define MCLK_PDM1 86 107 #define HCLK_SPDIF_TX0 87 108 #define MCLK_SPDIF_TX0 88 109 #define HCLK_SPDIF_TX1 89 110 #define MCLK_SPDIF_TX1 90 111 #define CLK_SAI1_MCLKOUT 91 112 #define CLK_SAI2_MCLKOUT 92 113 #define CLK_SAI3_MCLKOUT 93 114 #define CLK_SAI4_MCLKOUT 94 115 #define CLK_SAI0_MCLKOUT 95 116 #define HCLK_BUS_ROOT 96 117 #define PCLK_BUS_ROOT 97 118 #define ACLK_BUS_ROOT 98 119 #define HCLK_CAN0 99 120 #define CLK_CAN0 100 121 #define HCLK_CAN1 101 122 #define CLK_CAN1 102 123 #define CLK_KEY_SHIFT 103 124 #define PCLK_I2C1 104 125 #define PCLK_I2C2 105 126 #define PCLK_I2C3 106 127 #define PCLK_I2C4 107 128 #define PCLK_I2C5 108 129 #define PCLK_I2C6 109 130 #define PCLK_I2C7 110 131 #define PCLK_I2C8 111 132 #define PCLK_I2C9 112 133 #define PCLK_WDT_BUSMCU 113 134 #define TCLK_WDT_BUSMCU 114 135 #define ACLK_GIC 115 136 #define CLK_I2C1 116 137 #define CLK_I2C2 117 138 #define CLK_I2C3 118 139 #define CLK_I2C4 119 140 #define CLK_I2C5 120 141 #define CLK_I2C6 121 142 #define CLK_I2C7 122 143 #define CLK_I2C8 123 144 #define CLK_I2C9 124 145 #define PCLK_SARADC 125 146 #define CLK_SARADC 126 147 #define PCLK_TSADC 127 148 #define CLK_TSADC 128 149 #define PCLK_UART0 129 150 #define PCLK_UART2 130 151 #define PCLK_UART3 131 152 #define PCLK_UART4 132 153 #define PCLK_UART5 133 154 #define PCLK_UART6 134 155 #define PCLK_UART7 135 156 #define PCLK_UART8 136 157 #define PCLK_UART9 137 158 #define PCLK_UART10 138 159 #define PCLK_UART11 139 160 #define SCLK_UART0 140 161 #define SCLK_UART2 141 162 #define SCLK_UART3 142 163 #define SCLK_UART4 143 164 #define SCLK_UART5 144 165 #define SCLK_UART6 145 166 #define SCLK_UART7 146 167 #define SCLK_UART8 147 168 #define SCLK_UART9 148 169 #define SCLK_UART10 149 170 #define SCLK_UART11 150 171 #define PCLK_SPI0 151 172 #define PCLK_SPI1 152 173 #define PCLK_SPI2 153 174 #define PCLK_SPI3 154 175 #define PCLK_SPI4 155 176 #define CLK_SPI0 156 177 #define CLK_SPI1 157 178 #define CLK_SPI2 158 179 #define CLK_SPI3 159 180 #define CLK_SPI4 160 181 #define PCLK_WDT0 161 182 #define TCLK_WDT0 162 183 #define PCLK_PWM1 163 184 #define CLK_PWM1 164 185 #define CLK_OSC_PWM1 165 186 #define CLK_RC_PWM1 166 187 #define PCLK_BUSTIMER0 167 188 #define PCLK_BUSTIMER1 168 189 #define CLK_TIMER0_ROOT 169 190 #define CLK_TIMER0 170 191 #define CLK_TIMER1 171 192 #define CLK_TIMER2 172 193 #define CLK_TIMER3 173 194 #define CLK_TIMER4 174 195 #define CLK_TIMER5 175 196 #define PCLK_MAILBOX0 176 197 #define PCLK_GPIO1 177 198 #define DBCLK_GPIO1 178 199 #define PCLK_GPIO2 179 200 #define DBCLK_GPIO2 180 201 #define PCLK_GPIO3 181 202 #define DBCLK_GPIO3 182 203 #define PCLK_GPIO4 183 204 #define DBCLK_GPIO4 184 205 #define ACLK_DECOM 185 206 #define PCLK_DECOM 186 207 #define DCLK_DECOM 187 208 #define CLK_TIMER1_ROOT 188 209 #define CLK_TIMER6 189 210 #define CLK_TIMER7 190 211 #define CLK_TIMER8 191 212 #define CLK_TIMER9 192 213 #define CLK_TIMER10 193 214 #define CLK_TIMER11 194 215 #define ACLK_DMAC0 195 216 #define ACLK_DMAC1 196 217 #define ACLK_DMAC2 197 218 #define ACLK_SPINLOCK 198 219 #define HCLK_I3C0 199 220 #define HCLK_I3C1 200 221 #define HCLK_BUS_CM0_ROOT 201 222 #define FCLK_BUS_CM0_CORE 202 223 #define CLK_BUS_CM0_RTC 203 224 #define PCLK_PMU2 204 225 #define PCLK_PWM2 205 226 #define CLK_PWM2 206 227 #define CLK_RC_PWM2 207 228 #define CLK_OSC_PWM2 208 229 #define CLK_FREQ_PWM1 209 230 #define CLK_COUNTER_PWM1 210 231 #define SAI_SCLKIN_FREQ 211 232 #define SAI_SCLKIN_COUNTER 212 233 #define CLK_I3C0 213 234 #define CLK_I3C1 214 235 #define PCLK_CSIDPHY1 215 236 #define PCLK_DDR_ROOT 216 237 #define PCLK_DDR_MON_CH0 217 238 #define TMCLK_DDR_MON_CH0 218 239 #define ACLK_DDR_ROOT 219 240 #define HCLK_DDR_ROOT 220 241 #define FCLK_DDR_CM0_CORE 221 242 #define CLK_DDR_TIMER_ROOT 222 243 #define CLK_DDR_TIMER0 223 244 #define CLK_DDR_TIMER1 224 245 #define TCLK_WDT_DDR 225 246 #define PCLK_WDT 226 247 #define PCLK_TIMER 227 248 #define CLK_DDR_CM0_RTC 228 249 #define ACLK_RKNN0 229 250 #define ACLK_RKNN1 230 251 #define HCLK_RKNN_ROOT 231 252 #define CLK_RKNN_DSU0 232 253 #define PCLK_NPUTOP_ROOT 233 254 #define PCLK_NPU_TIMER 234 255 #define CLK_NPUTIMER_ROOT 235 256 #define CLK_NPUTIMER0 236 257 #define CLK_NPUTIMER1 237 258 #define PCLK_NPU_WDT 238 259 #define TCLK_NPU_WDT 239 260 #define ACLK_RKNN_CBUF 240 261 #define HCLK_NPU_CM0_ROOT 241 262 #define FCLK_NPU_CM0_CORE 242 263 #define CLK_NPU_CM0_RTC 243 264 #define HCLK_RKNN_CBUF 244 265 #define HCLK_NVM_ROOT 245 266 #define ACLK_NVM_ROOT 246 267 #define SCLK_FSPI_X2 247 268 #define HCLK_FSPI 248 269 #define CCLK_SRC_EMMC 249 270 #define HCLK_EMMC 250 271 #define ACLK_EMMC 251 272 #define BCLK_EMMC 252 273 #define TCLK_EMMC 253 274 #define PCLK_PHP_ROOT 254 275 #define ACLK_PHP_ROOT 255 276 #define PCLK_PCIE0 256 277 #define CLK_PCIE0_AUX 257 278 #define ACLK_PCIE0_MST 258 279 #define ACLK_PCIE0_SLV 259 280 #define ACLK_PCIE0_DBI 260 281 #define ACLK_USB3OTG1 261 282 #define CLK_REF_USB3OTG1 262 283 #define CLK_SUSPEND_USB3OTG1 263 284 #define ACLK_MMU0 264 285 #define ACLK_SLV_MMU0 265 286 #define ACLK_MMU1 266 287 #define ACLK_SLV_MMU1 267 288 #define PCLK_PCIE1 268 289 #define CLK_PCIE1_AUX 269 290 #define ACLK_PCIE1_MST 270 291 #define ACLK_PCIE1_SLV 271 292 #define ACLK_PCIE1_DBI 272 293 #define CLK_RXOOB0 273 294 #define CLK_RXOOB1 274 295 #define CLK_PMALIVE0 275 296 #define CLK_PMALIVE1 276 297 #define ACLK_SATA0 277 298 #define ACLK_SATA1 278 299 #define CLK_USB3OTG1_PIPE_PCLK 279 300 #define CLK_USB3OTG1_UTMI 280 301 #define CLK_USB3OTG0_PIPE_PCLK 281 302 #define CLK_USB3OTG0_UTMI 282 303 #define HCLK_SDGMAC_ROOT 283 304 #define ACLK_SDGMAC_ROOT 284 305 #define PCLK_SDGMAC_ROOT 285 306 #define ACLK_GMAC0 286 307 #define ACLK_GMAC1 287 308 #define PCLK_GMAC0 288 309 #define PCLK_GMAC1 289 310 #define CCLK_SRC_SDIO 290 311 #define HCLK_SDIO 291 312 #define CLK_GMAC1_PTP_REF 292 313 #define CLK_GMAC0_PTP_REF 293 314 #define CLK_GMAC1_PTP_REF_SRC 294 315 #define CLK_GMAC0_PTP_REF_SRC 295 316 #define CCLK_SRC_SDMMC0 296 317 #define HCLK_SDMMC0 297 318 #define SCLK_FSPI1_X2 298 319 #define HCLK_FSPI1 299 320 #define ACLK_DSMC_ROOT 300 321 #define ACLK_DSMC 301 322 #define PCLK_DSMC 302 323 #define CLK_DSMC_SYS 303 324 #define HCLK_HSGPIO 304 325 #define CLK_HSGPIO_TX 305 326 #define CLK_HSGPIO_RX 306 327 #define ACLK_HSGPIO 307 328 #define PCLK_PHPPHY_ROOT 308 329 #define PCLK_PCIE2_COMBOPHY0 309 330 #define PCLK_PCIE2_COMBOPHY1 310 331 #define CLK_PCIE_100M_SRC 311 332 #define CLK_PCIE_100M_NDUTY_SRC 312 333 #define CLK_REF_PCIE0_PHY 313 334 #define CLK_REF_PCIE1_PHY 314 335 #define CLK_REF_MPHY_26M 315 336 #define HCLK_RKVDEC_ROOT 316 337 #define ACLK_RKVDEC_ROOT 317 338 #define HCLK_RKVDEC 318 339 #define CLK_RKVDEC_HEVC_CA 319 340 #define CLK_RKVDEC_CORE 320 341 #define ACLK_UFS_ROOT 321 342 #define ACLK_USB_ROOT 322 343 #define PCLK_USB_ROOT 323 344 #define ACLK_USB3OTG0 324 345 #define CLK_REF_USB3OTG0 325 346 #define CLK_SUSPEND_USB3OTG0 326 347 #define ACLK_MMU2 327 348 #define ACLK_SLV_MMU2 328 349 #define ACLK_UFS_SYS 329 350 #define ACLK_VPU_ROOT 330 351 #define ACLK_VPU_MID_ROOT 331 352 #define HCLK_VPU_ROOT 332 353 #define ACLK_JPEG_ROOT 333 354 #define ACLK_VPU_LOW_ROOT 334 355 #define HCLK_RGA2E_0 335 356 #define ACLK_RGA2E_0 336 357 #define CLK_CORE_RGA2E_0 337 358 #define ACLK_JPEG 338 359 #define HCLK_JPEG 339 360 #define HCLK_VDPP 340 361 #define ACLK_VDPP 341 362 #define CLK_CORE_VDPP 342 363 #define HCLK_RGA2E_1 343 364 #define ACLK_RGA2E_1 344 365 #define CLK_CORE_RGA2E_1 345 366 #define DCLK_EBC_FRAC_SRC 346 367 #define HCLK_EBC 347 368 #define ACLK_EBC 348 369 #define DCLK_EBC 349 370 #define HCLK_VEPU0_ROOT 350 371 #define ACLK_VEPU0_ROOT 351 372 #define HCLK_VEPU0 352 373 #define ACLK_VEPU0 353 374 #define CLK_VEPU0_CORE 354 375 #define ACLK_VI_ROOT 355 376 #define HCLK_VI_ROOT 356 377 #define PCLK_VI_ROOT 357 378 #define DCLK_VICAP 358 379 #define ACLK_VICAP 359 380 #define HCLK_VICAP 360 381 #define CLK_ISP_CORE 361 382 #define CLK_ISP_CORE_MARVIN 362 383 #define CLK_ISP_CORE_VICAP 363 384 #define ACLK_ISP 364 385 #define HCLK_ISP 365 386 #define ACLK_VPSS 366 387 #define HCLK_VPSS 367 388 #define CLK_CORE_VPSS 368 389 #define PCLK_CSI_HOST_0 369 390 #define PCLK_CSI_HOST_1 370 391 #define PCLK_CSI_HOST_2 371 392 #define PCLK_CSI_HOST_3 372 393 #define PCLK_CSI_HOST_4 373 394 #define ICLK_CSIHOST01 374 395 #define ICLK_CSIHOST0 375 396 #define CLK_ISP_PVTPLL_SRC 376 397 #define ACLK_VI_ROOT_INTER 377 398 #define CLK_VICAP_I0CLK 378 399 #define CLK_VICAP_I1CLK 379 400 #define CLK_VICAP_I2CLK 380 401 #define CLK_VICAP_I3CLK 381 402 #define CLK_VICAP_I4CLK 382 403 #define ACLK_VOP_ROOT 383 404 #define HCLK_VOP_ROOT 384 405 #define PCLK_VOP_ROOT 385 406 #define HCLK_VOP 386 407 #define ACLK_VOP 387 408 #define DCLK_VP0_SRC 388 409 #define DCLK_VP1_SRC 389 410 #define DCLK_VP2_SRC 390 411 #define DCLK_VP0 391 412 #define DCLK_VP1 392 413 #define DCLK_VP2 393 414 #define PCLK_VOPGRF 394 415 #define ACLK_VO0_ROOT 395 416 #define HCLK_VO0_ROOT 396 417 #define PCLK_VO0_ROOT 397 418 #define PCLK_VO0_GRF 398 419 #define ACLK_HDCP0 399 420 #define HCLK_HDCP0 400 421 #define PCLK_HDCP0 401 422 #define CLK_TRNG0_SKP 402 423 #define PCLK_DSIHOST0 403 424 #define CLK_DSIHOST0 404 425 #define PCLK_HDMITX0 405 426 #define CLK_HDMITX0_EARC 406 427 #define CLK_HDMITX0_REF 407 428 #define PCLK_EDP0 408 429 #define CLK_EDP0_24M 409 430 #define CLK_EDP0_200M 410 431 #define MCLK_SAI5_8CH_SRC 411 432 #define MCLK_SAI5_8CH 412 433 #define HCLK_SAI5_8CH 413 434 #define MCLK_SAI6_8CH_SRC 414 435 #define MCLK_SAI6_8CH 415 436 #define HCLK_SAI6_8CH 416 437 #define HCLK_SPDIF_TX2 417 438 #define MCLK_SPDIF_TX2 418 439 #define HCLK_SPDIF_RX2 419 440 #define MCLK_SPDIF_RX2 420 441 #define HCLK_SAI8_8CH 421 442 #define MCLK_SAI8_8CH_SRC 422 443 #define MCLK_SAI8_8CH 423 444 #define ACLK_VO1_ROOT 424 445 #define HCLK_VO1_ROOT 425 446 #define PCLK_VO1_ROOT 426 447 #define MCLK_SAI7_8CH_SRC 427 448 #define MCLK_SAI7_8CH 428 449 #define HCLK_SAI7_8CH 429 450 #define HCLK_SPDIF_TX3 430 451 #define HCLK_SPDIF_TX4 431 452 #define HCLK_SPDIF_TX5 432 453 #define MCLK_SPDIF_TX3 433 454 #define CLK_AUX16MHZ_0 434 455 #define ACLK_DP0 435 456 #define PCLK_DP0 436 457 #define PCLK_VO1_GRF 437 458 #define ACLK_HDCP1 438 459 #define HCLK_HDCP1 439 460 #define PCLK_HDCP1 440 461 #define CLK_TRNG1_SKP 441 462 #define HCLK_SAI9_8CH 442 463 #define MCLK_SAI9_8CH_SRC 443 464 #define MCLK_SAI9_8CH 444 465 #define MCLK_SPDIF_TX4 445 466 #define MCLK_SPDIF_TX5 446 467 #define CLK_GPU_SRC_PRE 447 468 #define CLK_GPU 448 469 #define PCLK_GPU_ROOT 449 470 #define ACLK_CENTER_ROOT 450 471 #define ACLK_CENTER_LOW_ROOT 451 472 #define HCLK_CENTER_ROOT 452 473 #define PCLK_CENTER_ROOT 453 474 #define ACLK_DMA2DDR 454 475 #define ACLK_DDR_SHAREMEM 455 476 #define PCLK_DMA2DDR 456 477 #define PCLK_SHAREMEM 457 478 #define HCLK_VEPU1_ROOT 458 479 #define ACLK_VEPU1_ROOT 459 480 #define HCLK_VEPU1 460 481 #define ACLK_VEPU1 461 482 #define CLK_VEPU1_CORE 462 483 #define CLK_JDBCK_DAP 463 484 #define PCLK_MIPI_DCPHY 464 485 #define CLK_32K_USB2DEBUG 465 486 #define PCLK_CSIDPHY 466 487 #define PCLK_USBDPPHY 467 488 #define CLK_PMUPHY_REF_SRC 468 489 #define CLK_USBDP_COMBO_PHY_IMMORTAL 469 490 #define CLK_HDMITXHDP 470 491 #define PCLK_MPHY 471 492 #define CLK_REF_OSC_MPHY 472 493 #define CLK_REF_UFS_CLKOUT 473 494 #define HCLK_PMU1_ROOT 474 495 #define HCLK_PMU_CM0_ROOT 475 496 #define CLK_200M_PMU_SRC 476 497 #define CLK_100M_PMU_SRC 477 498 #define CLK_50M_PMU_SRC 478 499 #define FCLK_PMU_CM0_CORE 479 500 #define CLK_PMU_CM0_RTC 480 501 #define PCLK_PMU1 481 502 #define CLK_PMU1 482 503 #define PCLK_PMU1WDT 483 504 #define TCLK_PMU1WDT 484 505 #define PCLK_PMUTIMER 485 506 #define CLK_PMUTIMER_ROOT 486 507 #define CLK_PMUTIMER0 487 508 #define CLK_PMUTIMER1 488 509 #define PCLK_PMU1PWM 489 510 #define CLK_PMU1PWM 490 511 #define CLK_PMU1PWM_OSC 491 512 #define PCLK_PMUPHY_ROOT 492 513 #define PCLK_I2C0 493 514 #define CLK_I2C0 494 515 #define SCLK_UART1 495 516 #define PCLK_UART1 496 517 #define CLK_PMU1PWM_RC 497 518 #define CLK_PDM0 498 519 #define HCLK_PDM0 499 520 #define MCLK_PDM0 500 521 #define HCLK_VAD 501 522 #define CLK_OSCCHK_PVTM 502 523 #define CLK_PDM0_OUT 503 524 #define CLK_HPTIMER_SRC 504 525 #define PCLK_PMU0_ROOT 505 526 #define PCLK_PMU0 506 527 #define PCLK_GPIO0 507 528 #define DBCLK_GPIO0 508 529 #define CLK_OSC0_PMU1 509 530 #define PCLK_PMU1_ROOT 510 531 #define XIN_OSC0_DIV 511 532 #define ACLK_USB 512 533 #define ACLK_UFS 513 534 #define ACLK_SDGMAC 514 535 #define HCLK_SDGMAC 515 536 #define PCLK_SDGMAC 516 537 #define HCLK_VO1 517 538 #define HCLK_VO0 518 539 #define PCLK_CCI_ROOT 519 540 #define ACLK_CCI_ROOT 520 541 #define HCLK_VO0VOP_CHANNEL 521 542 #define ACLK_VO0VOP_CHANNEL 522 543 #define ACLK_TOP_MID 523 544 #define ACLK_SECURE_HIGH 524 545 #define CLK_USBPHY_REF_SRC 525 546 #define CLK_PHY_REF_SRC 526 547 #define CLK_CPLL_REF_SRC 527 548 #define CLK_AUPLL_REF_SRC 528 549 #define PCLK_SECURE_NS 529 550 #define HCLK_SECURE_NS 530 551 #define ACLK_SECURE_NS 531 552 #define PCLK_OTPC_NS 532 553 #define HCLK_CRYPTO_NS 533 554 #define HCLK_TRNG_NS 534 555 #define CLK_OTPC_NS 535 556 #define SCLK_DSU 536 557 #define SCLK_DDR 537 558 #define ACLK_CRYPTO_NS 538 559 #define CLK_PKA_CRYPTO_NS 539 560 #define ACLK_RKVDEC_ROOT_BAK 540 561 #define CLK_AUDIO_FRAC_0_SRC 541 562 #define CLK_AUDIO_FRAC_1_SRC 542 563 #define CLK_AUDIO_FRAC_2_SRC 543 564 #define CLK_AUDIO_FRAC_3_SRC 544 565 #define PCLK_HDPTX_APB 545 566 567 /* secure clk */ 568 #define CLK_STIMER0_ROOT 546 569 #define CLK_STIMER1_ROOT 547 570 #define PCLK_SECURE_S 548 571 #define HCLK_SECURE_S 549 572 #define ACLK_SECURE_S 550 573 #define CLK_PKA_CRYPTO_S 551 574 #define HCLK_VO1_S 552 575 #define PCLK_VO1_S 553 576 #define HCLK_VO0_S 554 577 #define PCLK_VO0_S 555 578 #define PCLK_KLAD 556 579 #define HCLK_CRYPTO_S 557 580 #define HCLK_KLAD 558 581 #define ACLK_CRYPTO_S 559 582 #define HCLK_TRNG_S 560 583 #define PCLK_OTPC_S 561 584 #define CLK_OTPC_S 562 585 #define PCLK_WDT_S 563 586 #define TCLK_WDT_S 564 587 #define PCLK_HDCP0_TRNG 565 588 #define PCLK_HDCP1_TRNG 566 589 #define HCLK_HDCP_KEY0 567 590 #define HCLK_HDCP_KEY1 568 591 #define PCLK_EDP_S 569 592 #define ACLK_KLAD 570 593 594 #endif 595
Indexes created Mon Apr 27 00:23:16 UTC 2026