1/* $NetBSD: sophgo,cv1800.h,v 1.1 2024/08/12 10:55:56 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ 4/* 5 * Copyright (C) 2023 Sophgo Ltd. 6 */ 7 8#ifndef __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ 9#define __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ 10 11#define CLK_MPLL 0 12#define CLK_TPLL 1 13#define CLK_FPLL 2 14#define CLK_MIPIMPLL 3 15#define CLK_A0PLL 4 16#define CLK_DISPPLL 5 17#define CLK_CAM0PLL 6 18#define CLK_CAM1PLL 7 19 20#define CLK_MIPIMPLL_D3 8 21#define CLK_CAM0PLL_D2 9 22#define CLK_CAM0PLL_D3 10 23 24#define CLK_TPU 11 25#define CLK_TPU_FAB 12 26#define CLK_AHB_ROM 13 27#define CLK_DDR_AXI_REG 14 28#define CLK_RTC_25M 15 29#define CLK_SRC_RTC_SYS_0 16 30#define CLK_TEMPSEN 17 31#define CLK_SARADC 18 32#define CLK_EFUSE 19 33#define CLK_APB_EFUSE 20 34#define CLK_DEBUG 21 35#define CLK_AP_DEBUG 22 36#define CLK_XTAL_MISC 23 37#define CLK_AXI4_EMMC 24 38#define CLK_EMMC 25 39#define CLK_EMMC_100K 26 40#define CLK_AXI4_SD0 27 41#define CLK_SD0 28 42#define CLK_SD0_100K 29 43#define CLK_AXI4_SD1 30 44#define CLK_SD1 31 45#define CLK_SD1_100K 32 46#define CLK_SPI_NAND 33 47#define CLK_ETH0_500M 34 48#define CLK_AXI4_ETH0 35 49#define CLK_ETH1_500M 36 50#define CLK_AXI4_ETH1 37 51#define CLK_APB_GPIO 38 52#define CLK_APB_GPIO_INTR 39 53#define CLK_GPIO_DB 40 54#define CLK_AHB_SF 41 55#define CLK_AHB_SF1 42 56#define CLK_A24M 43 57#define CLK_AUDSRC 44 58#define CLK_APB_AUDSRC 45 59#define CLK_SDMA_AXI 46 60#define CLK_SDMA_AUD0 47 61#define CLK_SDMA_AUD1 48 62#define CLK_SDMA_AUD2 49 63#define CLK_SDMA_AUD3 50 64#define CLK_I2C 51 65#define CLK_APB_I2C 52 66#define CLK_APB_I2C0 53 67#define CLK_APB_I2C1 54 68#define CLK_APB_I2C2 55 69#define CLK_APB_I2C3 56 70#define CLK_APB_I2C4 57 71#define CLK_APB_WDT 58 72#define CLK_PWM_SRC 59 73#define CLK_PWM 60 74#define CLK_SPI 61 75#define CLK_APB_SPI0 62 76#define CLK_APB_SPI1 63 77#define CLK_APB_SPI2 64 78#define CLK_APB_SPI3 65 79#define CLK_1M 66 80#define CLK_CAM0_200 67 81#define CLK_PM 68 82#define CLK_TIMER0 69 83#define CLK_TIMER1 70 84#define CLK_TIMER2 71 85#define CLK_TIMER3 72 86#define CLK_TIMER4 73 87#define CLK_TIMER5 74 88#define CLK_TIMER6 75 89#define CLK_TIMER7 76 90#define CLK_UART0 77 91#define CLK_APB_UART0 78 92#define CLK_UART1 79 93#define CLK_APB_UART1 80 94#define CLK_UART2 81 95#define CLK_APB_UART2 82 96#define CLK_UART3 83 97#define CLK_APB_UART3 84 98#define CLK_UART4 85 99#define CLK_APB_UART4 86 100#define CLK_APB_I2S0 87 101#define CLK_APB_I2S1 88 102#define CLK_APB_I2S2 89 103#define CLK_APB_I2S3 90 104#define CLK_AXI4_USB 91 105#define CLK_APB_USB 92 106#define CLK_USB_125M 93 107#define CLK_USB_33K 94 108#define CLK_USB_12M 95 109#define CLK_AXI4 96 110#define CLK_AXI6 97 111#define CLK_DSI_ESC 98 112#define CLK_AXI_VIP 99 113#define CLK_SRC_VIP_SYS_0 100 114#define CLK_SRC_VIP_SYS_1 101 115#define CLK_SRC_VIP_SYS_2 102 116#define CLK_SRC_VIP_SYS_3 103 117#define CLK_SRC_VIP_SYS_4 104 118#define CLK_CSI_BE_VIP 105 119#define CLK_CSI_MAC0_VIP 106 120#define CLK_CSI_MAC1_VIP 107 121#define CLK_CSI_MAC2_VIP 108 122#define CLK_CSI0_RX_VIP 109 123#define CLK_CSI1_RX_VIP 110 124#define CLK_ISP_TOP_VIP 111 125#define CLK_IMG_D_VIP 112 126#define CLK_IMG_V_VIP 113 127#define CLK_SC_TOP_VIP 114 128#define CLK_SC_D_VIP 115 129#define CLK_SC_V1_VIP 116 130#define CLK_SC_V2_VIP 117 131#define CLK_SC_V3_VIP 118 132#define CLK_DWA_VIP 119 133#define CLK_BT_VIP 120 134#define CLK_DISP_VIP 121 135#define CLK_DSI_MAC_VIP 122 136#define CLK_LVDS0_VIP 123 137#define CLK_LVDS1_VIP 124 138#define CLK_PAD_VI_VIP 125 139#define CLK_PAD_VI1_VIP 126 140#define CLK_PAD_VI2_VIP 127 141#define CLK_CFG_REG_VIP 128 142#define CLK_VIP_IP0 129 143#define CLK_VIP_IP1 130 144#define CLK_VIP_IP2 131 145#define CLK_VIP_IP3 132 146#define CLK_IVE_VIP 133 147#define CLK_RAW_VIP 134 148#define CLK_OSDC_VIP 135 149#define CLK_CAM0_VIP 136 150#define CLK_AXI_VIDEO_CODEC 137 151#define CLK_VC_SRC0 138 152#define CLK_VC_SRC1 139 153#define CLK_VC_SRC2 140 154#define CLK_H264C 141 155#define CLK_APB_H264C 142 156#define CLK_H265C 143 157#define CLK_APB_H265C 144 158#define CLK_JPEG 145 159#define CLK_APB_JPEG 146 160#define CLK_CAM0 147 161#define CLK_CAM1 148 162#define CLK_WGN 149 163#define CLK_WGN0 150 164#define CLK_WGN1 151 165#define CLK_WGN2 152 166#define CLK_KEYSCAN 153 167#define CLK_CFG_REG_VC 154 168#define CLK_C906_0 155 169#define CLK_C906_1 156 170#define CLK_A53 157 171#define CLK_CPU_AXI0 158 172#define CLK_CPU_GIC 159 173#define CLK_XTAL_AP 160 174 175// Only for CV181x 176#define CLK_DISP_SRC_VIP 161 177 178#endif /* __DT_BINDINGS_SOPHGO_CV1800_CLK_H__ */ 179