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      1 /*	$NetBSD: stm32fx-clock.h,v 1.1.1.3 2020/01/03 14:33:05 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0-only */
      4 /*
      5  * stm32fx-clock.h
      6  *
      7  * Copyright (C) 2016 STMicroelectronics
      8  * Author: Gabriel Fernandez for STMicroelectronics.
      9  */
     10 
     11 /*
     12  * List of clocks wich are not derived from system clock (SYSCLOCK)
     13  *
     14  * The index of these clocks is the secondary index of DT bindings
     15  * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
     16  *
     17  * e.g:
     18 	<assigned-clocks = <&rcc 1 CLK_LSE>;
     19 */
     20 
     21 #ifndef _DT_BINDINGS_CLK_STMFX_H
     22 #define _DT_BINDINGS_CLK_STMFX_H
     23 
     24 #define SYSTICK			0
     25 #define FCLK			1
     26 #define CLK_LSI			2
     27 #define CLK_LSE			3
     28 #define CLK_HSE_RTC		4
     29 #define CLK_RTC			5
     30 #define PLL_VCO_I2S		6
     31 #define PLL_VCO_SAI		7
     32 #define CLK_LCD			8
     33 #define CLK_I2S			9
     34 #define CLK_SAI1		10
     35 #define CLK_SAI2		11
     36 #define CLK_I2SQ_PDIV		12
     37 #define CLK_SAIQ_PDIV		13
     38 #define CLK_HSI			14
     39 #define CLK_SYSCLK		15
     40 #define CLK_F469_DSI		16
     41 
     42 #define END_PRIMARY_CLK		17
     43 
     44 #define CLK_HDMI_CEC		16
     45 #define CLK_SPDIF		17
     46 #define CLK_USART1		18
     47 #define CLK_USART2		19
     48 #define CLK_USART3		20
     49 #define CLK_UART4		21
     50 #define CLK_UART5		22
     51 #define CLK_USART6		23
     52 #define CLK_UART7		24
     53 #define CLK_UART8		25
     54 #define CLK_I2C1		26
     55 #define CLK_I2C2		27
     56 #define CLK_I2C3		28
     57 #define CLK_I2C4		29
     58 #define CLK_LPTIMER		30
     59 #define CLK_PLL_SRC		31
     60 #define CLK_DFSDM1		32
     61 #define CLK_ADFSDM1		33
     62 #define CLK_F769_DSI		34
     63 #define END_PRIMARY_CLK_F7	35
     64 
     65 #endif
     66