1/*	$NetBSD: sunplus,sp7021-clkc.h,v 1.1.1.1 2026/01/18 05:21:42 skrll Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
4/*
5 * Copyright (C) Sunplus Technology Co., Ltd.
6 *       All rights reserved.
7 */
8#ifndef _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
9#define _DT_BINDINGS_CLOCK_SUNPLUS_SP7021_H
10
11/* gates */
12#define CLK_RTC         0
13#define CLK_OTPRX       1
14#define CLK_NOC         2
15#define CLK_BR          3
16#define CLK_SPIFL       4
17#define CLK_PERI0       5
18#define CLK_PERI1       6
19#define CLK_STC0        7
20#define CLK_STC_AV0     8
21#define CLK_STC_AV1     9
22#define CLK_STC_AV2     10
23#define CLK_UA0         11
24#define CLK_UA1         12
25#define CLK_UA2         13
26#define CLK_UA3         14
27#define CLK_UA4         15
28#define CLK_HWUA        16
29#define CLK_DDC0        17
30#define CLK_UADMA       18
31#define CLK_CBDMA0      19
32#define CLK_CBDMA1      20
33#define CLK_SPI_COMBO_0 21
34#define CLK_SPI_COMBO_1 22
35#define CLK_SPI_COMBO_2 23
36#define CLK_SPI_COMBO_3 24
37#define CLK_AUD         25
38#define CLK_USBC0       26
39#define CLK_USBC1       27
40#define CLK_UPHY0       28
41#define CLK_UPHY1       29
42#define CLK_I2CM0       30
43#define CLK_I2CM1       31
44#define CLK_I2CM2       32
45#define CLK_I2CM3       33
46#define CLK_PMC         34
47#define CLK_CARD_CTL0   35
48#define CLK_CARD_CTL1   36
49#define CLK_CARD_CTL4   37
50#define CLK_BCH         38
51#define CLK_DDFCH       39
52#define CLK_CSIIW0      40
53#define CLK_CSIIW1      41
54#define CLK_MIPICSI0    42
55#define CLK_MIPICSI1    43
56#define CLK_HDMI_TX     44
57#define CLK_VPOST       45
58#define CLK_TGEN        46
59#define CLK_DMIX        47
60#define CLK_TCON        48
61#define CLK_GPIO        49
62#define CLK_MAILBOX     50
63#define CLK_SPIND       51
64#define CLK_I2C2CBUS    52
65#define CLK_SEC         53
66#define CLK_DVE         54
67#define CLK_GPOST0      55
68#define CLK_OSD0        56
69#define CLK_DISP_PWM    57
70#define CLK_UADBG       58
71#define CLK_FIO_CTL     59
72#define CLK_FPGA        60
73#define CLK_L2SW        61
74#define CLK_ICM         62
75#define CLK_AXI_GLOBAL  63
76
77/* plls */
78#define PLL_A           64
79#define PLL_E           65
80#define PLL_E_2P5       66
81#define PLL_E_25        67
82#define PLL_E_112P5     68
83#define PLL_F           69
84#define PLL_TV          70
85#define PLL_TV_A        71
86#define PLL_SYS         72
87
88#define CLK_MAX         73
89
90#endif
91