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      1      1.1  jmcneill /*	$NetBSD: tegra114-car.h,v 1.1.1.4 2021/11/07 16:49:59 jmcneill Exp $	*/
      2      1.1  jmcneill 
      3  1.1.1.3  jmcneill /* SPDX-License-Identifier: GPL-2.0 */
      4      1.1  jmcneill /*
      5      1.1  jmcneill  * This header provides constants for binding nvidia,tegra114-car.
      6      1.1  jmcneill  *
      7      1.1  jmcneill  * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
      8      1.1  jmcneill  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
      9      1.1  jmcneill  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
     10      1.1  jmcneill  * this case, those clocks are assigned IDs above 160 in order to highlight
     11      1.1  jmcneill  * this issue. Implementations that interpret these clock IDs as bit values
     12      1.1  jmcneill  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
     13      1.1  jmcneill  * explicitly handle these special cases.
     14      1.1  jmcneill  *
     15      1.1  jmcneill  * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
     16      1.1  jmcneill  * above.
     17      1.1  jmcneill  */
     18      1.1  jmcneill 
     19      1.1  jmcneill #ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
     20      1.1  jmcneill #define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H
     21      1.1  jmcneill 
     22      1.1  jmcneill /* 0 */
     23      1.1  jmcneill /* 1 */
     24      1.1  jmcneill /* 2 */
     25      1.1  jmcneill /* 3 */
     26      1.1  jmcneill #define TEGRA114_CLK_RTC 4
     27      1.1  jmcneill #define TEGRA114_CLK_TIMER 5
     28      1.1  jmcneill #define TEGRA114_CLK_UARTA 6
     29      1.1  jmcneill /* 7 (register bit affects uartb and vfir) */
     30      1.1  jmcneill /* 8 */
     31      1.1  jmcneill #define TEGRA114_CLK_SDMMC2 9
     32      1.1  jmcneill /* 10 (register bit affects spdif_in and spdif_out) */
     33      1.1  jmcneill #define TEGRA114_CLK_I2S1 11
     34      1.1  jmcneill #define TEGRA114_CLK_I2C1 12
     35      1.1  jmcneill #define TEGRA114_CLK_NDFLASH 13
     36      1.1  jmcneill #define TEGRA114_CLK_SDMMC1 14
     37      1.1  jmcneill #define TEGRA114_CLK_SDMMC4 15
     38      1.1  jmcneill /* 16 */
     39      1.1  jmcneill #define TEGRA114_CLK_PWM 17
     40      1.1  jmcneill #define TEGRA114_CLK_I2S2 18
     41      1.1  jmcneill #define TEGRA114_CLK_EPP 19
     42      1.1  jmcneill /* 20 (register bit affects vi and vi_sensor) */
     43      1.1  jmcneill #define TEGRA114_CLK_GR2D 21
     44      1.1  jmcneill #define TEGRA114_CLK_USBD 22
     45      1.1  jmcneill #define TEGRA114_CLK_ISP 23
     46      1.1  jmcneill #define TEGRA114_CLK_GR3D 24
     47      1.1  jmcneill /* 25 */
     48      1.1  jmcneill #define TEGRA114_CLK_DISP2 26
     49      1.1  jmcneill #define TEGRA114_CLK_DISP1 27
     50      1.1  jmcneill #define TEGRA114_CLK_HOST1X 28
     51      1.1  jmcneill #define TEGRA114_CLK_VCP 29
     52      1.1  jmcneill #define TEGRA114_CLK_I2S0 30
     53      1.1  jmcneill /* 31 */
     54      1.1  jmcneill 
     55      1.1  jmcneill #define TEGRA114_CLK_MC 32
     56      1.1  jmcneill /* 33 */
     57      1.1  jmcneill #define TEGRA114_CLK_APBDMA 34
     58      1.1  jmcneill /* 35 */
     59      1.1  jmcneill #define TEGRA114_CLK_KBC 36
     60      1.1  jmcneill /* 37 */
     61      1.1  jmcneill /* 38 */
     62      1.1  jmcneill /* 39 (register bit affects fuse and fuse_burn) */
     63      1.1  jmcneill #define TEGRA114_CLK_KFUSE 40
     64      1.1  jmcneill #define TEGRA114_CLK_SBC1 41
     65      1.1  jmcneill #define TEGRA114_CLK_NOR 42
     66      1.1  jmcneill /* 43 */
     67      1.1  jmcneill #define TEGRA114_CLK_SBC2 44
     68      1.1  jmcneill /* 45 */
     69      1.1  jmcneill #define TEGRA114_CLK_SBC3 46
     70      1.1  jmcneill #define TEGRA114_CLK_I2C5 47
     71      1.1  jmcneill #define TEGRA114_CLK_DSIA 48
     72      1.1  jmcneill /* 49 */
     73      1.1  jmcneill #define TEGRA114_CLK_MIPI 50
     74      1.1  jmcneill #define TEGRA114_CLK_HDMI 51
     75      1.1  jmcneill #define TEGRA114_CLK_CSI 52
     76      1.1  jmcneill /* 53 */
     77      1.1  jmcneill #define TEGRA114_CLK_I2C2 54
     78      1.1  jmcneill #define TEGRA114_CLK_UARTC 55
     79      1.1  jmcneill #define TEGRA114_CLK_MIPI_CAL 56
     80      1.1  jmcneill #define TEGRA114_CLK_EMC 57
     81      1.1  jmcneill #define TEGRA114_CLK_USB2 58
     82      1.1  jmcneill #define TEGRA114_CLK_USB3 59
     83      1.1  jmcneill /* 60 */
     84      1.1  jmcneill #define TEGRA114_CLK_VDE 61
     85      1.1  jmcneill #define TEGRA114_CLK_BSEA 62
     86      1.1  jmcneill #define TEGRA114_CLK_BSEV 63
     87      1.1  jmcneill 
     88      1.1  jmcneill /* 64 */
     89      1.1  jmcneill #define TEGRA114_CLK_UARTD 65
     90      1.1  jmcneill /* 66 */
     91      1.1  jmcneill #define TEGRA114_CLK_I2C3 67
     92      1.1  jmcneill #define TEGRA114_CLK_SBC4 68
     93      1.1  jmcneill #define TEGRA114_CLK_SDMMC3 69
     94      1.1  jmcneill /* 70 */
     95      1.1  jmcneill #define TEGRA114_CLK_OWR 71
     96      1.1  jmcneill /* 72 */
     97      1.1  jmcneill #define TEGRA114_CLK_CSITE 73
     98      1.1  jmcneill /* 74 */
     99      1.1  jmcneill /* 75 */
    100      1.1  jmcneill #define TEGRA114_CLK_LA 76
    101      1.1  jmcneill #define TEGRA114_CLK_TRACE 77
    102      1.1  jmcneill #define TEGRA114_CLK_SOC_THERM 78
    103      1.1  jmcneill #define TEGRA114_CLK_DTV 79
    104      1.1  jmcneill #define TEGRA114_CLK_NDSPEED 80
    105      1.1  jmcneill #define TEGRA114_CLK_I2CSLOW 81
    106      1.1  jmcneill #define TEGRA114_CLK_DSIB 82
    107      1.1  jmcneill #define TEGRA114_CLK_TSEC 83
    108      1.1  jmcneill /* 84 */
    109      1.1  jmcneill /* 85 */
    110      1.1  jmcneill /* 86 */
    111      1.1  jmcneill /* 87 */
    112      1.1  jmcneill /* 88 */
    113      1.1  jmcneill #define TEGRA114_CLK_XUSB_HOST 89
    114      1.1  jmcneill /* 90 */
    115      1.1  jmcneill #define TEGRA114_CLK_MSENC 91
    116      1.1  jmcneill #define TEGRA114_CLK_CSUS 92
    117      1.1  jmcneill /* 93 */
    118      1.1  jmcneill /* 94 */
    119      1.1  jmcneill /* 95 (bit affects xusb_dev and xusb_dev_src) */
    120      1.1  jmcneill 
    121      1.1  jmcneill /* 96 */
    122      1.1  jmcneill /* 97 */
    123      1.1  jmcneill /* 98 */
    124      1.1  jmcneill #define TEGRA114_CLK_MSELECT 99
    125      1.1  jmcneill #define TEGRA114_CLK_TSENSOR 100
    126      1.1  jmcneill #define TEGRA114_CLK_I2S3 101
    127      1.1  jmcneill #define TEGRA114_CLK_I2S4 102
    128      1.1  jmcneill #define TEGRA114_CLK_I2C4 103
    129      1.1  jmcneill #define TEGRA114_CLK_SBC5 104
    130      1.1  jmcneill #define TEGRA114_CLK_SBC6 105
    131      1.1  jmcneill #define TEGRA114_CLK_D_AUDIO 106
    132      1.1  jmcneill #define TEGRA114_CLK_APBIF 107
    133      1.1  jmcneill #define TEGRA114_CLK_DAM0 108
    134      1.1  jmcneill #define TEGRA114_CLK_DAM1 109
    135      1.1  jmcneill #define TEGRA114_CLK_DAM2 110
    136      1.1  jmcneill #define TEGRA114_CLK_HDA2CODEC_2X 111
    137      1.1  jmcneill /* 112 */
    138      1.1  jmcneill #define TEGRA114_CLK_AUDIO0_2X 113
    139      1.1  jmcneill #define TEGRA114_CLK_AUDIO1_2X 114
    140      1.1  jmcneill #define TEGRA114_CLK_AUDIO2_2X 115
    141      1.1  jmcneill #define TEGRA114_CLK_AUDIO3_2X 116
    142      1.1  jmcneill #define TEGRA114_CLK_AUDIO4_2X 117
    143      1.1  jmcneill #define TEGRA114_CLK_SPDIF_2X 118
    144      1.1  jmcneill #define TEGRA114_CLK_ACTMON 119
    145      1.1  jmcneill #define TEGRA114_CLK_EXTERN1 120
    146      1.1  jmcneill #define TEGRA114_CLK_EXTERN2 121
    147      1.1  jmcneill #define TEGRA114_CLK_EXTERN3 122
    148      1.1  jmcneill /* 123 */
    149      1.1  jmcneill /* 124 */
    150      1.1  jmcneill #define TEGRA114_CLK_HDA 125
    151      1.1  jmcneill /* 126 */
    152      1.1  jmcneill #define TEGRA114_CLK_SE 127
    153      1.1  jmcneill 
    154      1.1  jmcneill #define TEGRA114_CLK_HDA2HDMI 128
    155      1.1  jmcneill /* 129 */
    156      1.1  jmcneill /* 130 */
    157      1.1  jmcneill /* 131 */
    158      1.1  jmcneill /* 132 */
    159      1.1  jmcneill /* 133 */
    160      1.1  jmcneill /* 134 */
    161      1.1  jmcneill /* 135 */
    162  1.1.1.2  jmcneill #define TEGRA114_CLK_CEC 136
    163      1.1  jmcneill /* 137 */
    164      1.1  jmcneill /* 138 */
    165      1.1  jmcneill /* 139 */
    166      1.1  jmcneill /* 140 */
    167      1.1  jmcneill /* 141 */
    168      1.1  jmcneill /* 142 */
    169      1.1  jmcneill /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
    170      1.1  jmcneill /*      xusb_host_src and xusb_ss_src) */
    171      1.1  jmcneill #define TEGRA114_CLK_CILAB 144
    172      1.1  jmcneill #define TEGRA114_CLK_CILCD 145
    173      1.1  jmcneill #define TEGRA114_CLK_CILE 146
    174      1.1  jmcneill #define TEGRA114_CLK_DSIALP 147
    175      1.1  jmcneill #define TEGRA114_CLK_DSIBLP 148
    176      1.1  jmcneill /* 149 */
    177      1.1  jmcneill #define TEGRA114_CLK_DDS 150
    178      1.1  jmcneill /* 151 */
    179      1.1  jmcneill #define TEGRA114_CLK_DP2 152
    180      1.1  jmcneill #define TEGRA114_CLK_AMX 153
    181      1.1  jmcneill #define TEGRA114_CLK_ADX 154
    182      1.1  jmcneill /* 155 (bit affects dfll_ref and dfll_soc) */
    183      1.1  jmcneill #define TEGRA114_CLK_XUSB_SS 156
    184      1.1  jmcneill /* 157 */
    185      1.1  jmcneill /* 158 */
    186      1.1  jmcneill /* 159 */
    187      1.1  jmcneill 
    188      1.1  jmcneill /* 160 */
    189      1.1  jmcneill /* 161 */
    190      1.1  jmcneill /* 162 */
    191      1.1  jmcneill /* 163 */
    192      1.1  jmcneill /* 164 */
    193      1.1  jmcneill /* 165 */
    194      1.1  jmcneill /* 166 */
    195      1.1  jmcneill /* 167 */
    196      1.1  jmcneill /* 168 */
    197      1.1  jmcneill /* 169 */
    198      1.1  jmcneill /* 170 */
    199      1.1  jmcneill /* 171 */
    200      1.1  jmcneill /* 172 */
    201      1.1  jmcneill /* 173 */
    202      1.1  jmcneill /* 174 */
    203      1.1  jmcneill /* 175 */
    204      1.1  jmcneill /* 176 */
    205      1.1  jmcneill /* 177 */
    206      1.1  jmcneill /* 178 */
    207      1.1  jmcneill /* 179 */
    208      1.1  jmcneill /* 180 */
    209      1.1  jmcneill /* 181 */
    210      1.1  jmcneill /* 182 */
    211      1.1  jmcneill /* 183 */
    212      1.1  jmcneill /* 184 */
    213      1.1  jmcneill /* 185 */
    214      1.1  jmcneill /* 186 */
    215      1.1  jmcneill /* 187 */
    216      1.1  jmcneill /* 188 */
    217      1.1  jmcneill /* 189 */
    218      1.1  jmcneill /* 190 */
    219      1.1  jmcneill /* 191 */
    220      1.1  jmcneill 
    221      1.1  jmcneill #define TEGRA114_CLK_UARTB 192
    222      1.1  jmcneill #define TEGRA114_CLK_VFIR 193
    223      1.1  jmcneill #define TEGRA114_CLK_SPDIF_IN 194
    224      1.1  jmcneill #define TEGRA114_CLK_SPDIF_OUT 195
    225      1.1  jmcneill #define TEGRA114_CLK_VI 196
    226      1.1  jmcneill #define TEGRA114_CLK_VI_SENSOR 197
    227      1.1  jmcneill #define TEGRA114_CLK_FUSE 198
    228      1.1  jmcneill #define TEGRA114_CLK_FUSE_BURN 199
    229      1.1  jmcneill #define TEGRA114_CLK_CLK_32K 200
    230      1.1  jmcneill #define TEGRA114_CLK_CLK_M 201
    231      1.1  jmcneill #define TEGRA114_CLK_CLK_M_DIV2 202
    232      1.1  jmcneill #define TEGRA114_CLK_CLK_M_DIV4 203
    233  1.1.1.4  jmcneill #define TEGRA114_CLK_OSC_DIV2 202
    234  1.1.1.4  jmcneill #define TEGRA114_CLK_OSC_DIV4 203
    235      1.1  jmcneill #define TEGRA114_CLK_PLL_REF 204
    236      1.1  jmcneill #define TEGRA114_CLK_PLL_C 205
    237      1.1  jmcneill #define TEGRA114_CLK_PLL_C_OUT1 206
    238      1.1  jmcneill #define TEGRA114_CLK_PLL_C2 207
    239      1.1  jmcneill #define TEGRA114_CLK_PLL_C3 208
    240      1.1  jmcneill #define TEGRA114_CLK_PLL_M 209
    241      1.1  jmcneill #define TEGRA114_CLK_PLL_M_OUT1 210
    242      1.1  jmcneill #define TEGRA114_CLK_PLL_P 211
    243      1.1  jmcneill #define TEGRA114_CLK_PLL_P_OUT1 212
    244      1.1  jmcneill #define TEGRA114_CLK_PLL_P_OUT2 213
    245      1.1  jmcneill #define TEGRA114_CLK_PLL_P_OUT3 214
    246      1.1  jmcneill #define TEGRA114_CLK_PLL_P_OUT4 215
    247      1.1  jmcneill #define TEGRA114_CLK_PLL_A 216
    248      1.1  jmcneill #define TEGRA114_CLK_PLL_A_OUT0 217
    249      1.1  jmcneill #define TEGRA114_CLK_PLL_D 218
    250      1.1  jmcneill #define TEGRA114_CLK_PLL_D_OUT0 219
    251      1.1  jmcneill #define TEGRA114_CLK_PLL_D2 220
    252      1.1  jmcneill #define TEGRA114_CLK_PLL_D2_OUT0 221
    253      1.1  jmcneill #define TEGRA114_CLK_PLL_U 222
    254      1.1  jmcneill #define TEGRA114_CLK_PLL_U_480M 223
    255      1.1  jmcneill 
    256      1.1  jmcneill #define TEGRA114_CLK_PLL_U_60M 224
    257      1.1  jmcneill #define TEGRA114_CLK_PLL_U_48M 225
    258      1.1  jmcneill #define TEGRA114_CLK_PLL_U_12M 226
    259      1.1  jmcneill #define TEGRA114_CLK_PLL_X 227
    260      1.1  jmcneill #define TEGRA114_CLK_PLL_X_OUT0 228
    261      1.1  jmcneill #define TEGRA114_CLK_PLL_RE_VCO 229
    262      1.1  jmcneill #define TEGRA114_CLK_PLL_RE_OUT 230
    263      1.1  jmcneill #define TEGRA114_CLK_PLL_E_OUT0 231
    264      1.1  jmcneill #define TEGRA114_CLK_SPDIF_IN_SYNC 232
    265      1.1  jmcneill #define TEGRA114_CLK_I2S0_SYNC 233
    266      1.1  jmcneill #define TEGRA114_CLK_I2S1_SYNC 234
    267      1.1  jmcneill #define TEGRA114_CLK_I2S2_SYNC 235
    268      1.1  jmcneill #define TEGRA114_CLK_I2S3_SYNC 236
    269      1.1  jmcneill #define TEGRA114_CLK_I2S4_SYNC 237
    270      1.1  jmcneill #define TEGRA114_CLK_VIMCLK_SYNC 238
    271      1.1  jmcneill #define TEGRA114_CLK_AUDIO0 239
    272      1.1  jmcneill #define TEGRA114_CLK_AUDIO1 240
    273      1.1  jmcneill #define TEGRA114_CLK_AUDIO2 241
    274      1.1  jmcneill #define TEGRA114_CLK_AUDIO3 242
    275      1.1  jmcneill #define TEGRA114_CLK_AUDIO4 243
    276      1.1  jmcneill #define TEGRA114_CLK_SPDIF 244
    277  1.1.1.4  jmcneill /* 245 */
    278  1.1.1.4  jmcneill /* 246 */
    279  1.1.1.4  jmcneill /* 247 */
    280  1.1.1.4  jmcneill /* 248 */
    281  1.1.1.4  jmcneill #define TEGRA114_CLK_OSC 249
    282      1.1  jmcneill /* 250 */
    283      1.1  jmcneill /* 251 */
    284      1.1  jmcneill #define TEGRA114_CLK_XUSB_HOST_SRC 252
    285      1.1  jmcneill #define TEGRA114_CLK_XUSB_FALCON_SRC 253
    286      1.1  jmcneill #define TEGRA114_CLK_XUSB_FS_SRC 254
    287      1.1  jmcneill #define TEGRA114_CLK_XUSB_SS_SRC 255
    288      1.1  jmcneill 
    289      1.1  jmcneill #define TEGRA114_CLK_XUSB_DEV_SRC 256
    290      1.1  jmcneill #define TEGRA114_CLK_XUSB_DEV 257
    291      1.1  jmcneill #define TEGRA114_CLK_XUSB_HS_SRC 258
    292      1.1  jmcneill #define TEGRA114_CLK_SCLK 259
    293      1.1  jmcneill #define TEGRA114_CLK_HCLK 260
    294      1.1  jmcneill #define TEGRA114_CLK_PCLK 261
    295      1.1  jmcneill #define TEGRA114_CLK_CCLK_G 262
    296      1.1  jmcneill #define TEGRA114_CLK_CCLK_LP 263
    297      1.1  jmcneill #define TEGRA114_CLK_DFLL_REF 264
    298      1.1  jmcneill #define TEGRA114_CLK_DFLL_SOC 265
    299      1.1  jmcneill /* 266 */
    300      1.1  jmcneill /* 267 */
    301      1.1  jmcneill /* 268 */
    302      1.1  jmcneill /* 269 */
    303      1.1  jmcneill /* 270 */
    304      1.1  jmcneill /* 271 */
    305      1.1  jmcneill /* 272 */
    306      1.1  jmcneill /* 273 */
    307      1.1  jmcneill /* 274 */
    308      1.1  jmcneill /* 275 */
    309      1.1  jmcneill /* 276 */
    310      1.1  jmcneill /* 277 */
    311      1.1  jmcneill /* 278 */
    312      1.1  jmcneill /* 279 */
    313      1.1  jmcneill /* 280 */
    314      1.1  jmcneill /* 281 */
    315      1.1  jmcneill /* 282 */
    316      1.1  jmcneill /* 283 */
    317      1.1  jmcneill /* 284 */
    318      1.1  jmcneill /* 285 */
    319      1.1  jmcneill /* 286 */
    320      1.1  jmcneill /* 287 */
    321      1.1  jmcneill 
    322      1.1  jmcneill /* 288 */
    323      1.1  jmcneill /* 289 */
    324      1.1  jmcneill /* 290 */
    325      1.1  jmcneill /* 291 */
    326      1.1  jmcneill /* 292 */
    327      1.1  jmcneill /* 293 */
    328      1.1  jmcneill /* 294 */
    329      1.1  jmcneill /* 295 */
    330      1.1  jmcneill /* 296 */
    331      1.1  jmcneill /* 297 */
    332      1.1  jmcneill /* 298 */
    333      1.1  jmcneill /* 299 */
    334      1.1  jmcneill #define TEGRA114_CLK_AUDIO0_MUX 300
    335      1.1  jmcneill #define TEGRA114_CLK_AUDIO1_MUX 301
    336      1.1  jmcneill #define TEGRA114_CLK_AUDIO2_MUX 302
    337      1.1  jmcneill #define TEGRA114_CLK_AUDIO3_MUX 303
    338      1.1  jmcneill #define TEGRA114_CLK_AUDIO4_MUX 304
    339      1.1  jmcneill #define TEGRA114_CLK_SPDIF_MUX 305
    340  1.1.1.4  jmcneill /* 306 */
    341  1.1.1.4  jmcneill /* 307 */
    342  1.1.1.4  jmcneill /* 308 */
    343      1.1  jmcneill #define TEGRA114_CLK_DSIA_MUX 309
    344      1.1  jmcneill #define TEGRA114_CLK_DSIB_MUX 310
    345      1.1  jmcneill #define TEGRA114_CLK_XUSB_SS_DIV2 311
    346      1.1  jmcneill #define TEGRA114_CLK_CLK_MAX 312
    347      1.1  jmcneill 
    348      1.1  jmcneill #endif	/* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
    349