1 /* $NetBSD: tegra114-car.h,v 1.1.1.4 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * This header provides constants for binding nvidia,tegra114-car. 6 * 7 * The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 8 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 9 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 10 * this case, those clocks are assigned IDs above 160 in order to highlight 11 * this issue. Implementations that interpret these clock IDs as bit values 12 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 13 * explicitly handle these special cases. 14 * 15 * The balance of the clocks controlled by the CAR are assigned IDs of 160 and 16 * above. 17 */ 18 19 #ifndef _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 20 #define _DT_BINDINGS_CLOCK_TEGRA114_CAR_H 21 22 /* 0 */ 23 /* 1 */ 24 /* 2 */ 25 /* 3 */ 26 #define TEGRA114_CLK_RTC 4 27 #define TEGRA114_CLK_TIMER 5 28 #define TEGRA114_CLK_UARTA 6 29 /* 7 (register bit affects uartb and vfir) */ 30 /* 8 */ 31 #define TEGRA114_CLK_SDMMC2 9 32 /* 10 (register bit affects spdif_in and spdif_out) */ 33 #define TEGRA114_CLK_I2S1 11 34 #define TEGRA114_CLK_I2C1 12 35 #define TEGRA114_CLK_NDFLASH 13 36 #define TEGRA114_CLK_SDMMC1 14 37 #define TEGRA114_CLK_SDMMC4 15 38 /* 16 */ 39 #define TEGRA114_CLK_PWM 17 40 #define TEGRA114_CLK_I2S2 18 41 #define TEGRA114_CLK_EPP 19 42 /* 20 (register bit affects vi and vi_sensor) */ 43 #define TEGRA114_CLK_GR2D 21 44 #define TEGRA114_CLK_USBD 22 45 #define TEGRA114_CLK_ISP 23 46 #define TEGRA114_CLK_GR3D 24 47 /* 25 */ 48 #define TEGRA114_CLK_DISP2 26 49 #define TEGRA114_CLK_DISP1 27 50 #define TEGRA114_CLK_HOST1X 28 51 #define TEGRA114_CLK_VCP 29 52 #define TEGRA114_CLK_I2S0 30 53 /* 31 */ 54 55 #define TEGRA114_CLK_MC 32 56 /* 33 */ 57 #define TEGRA114_CLK_APBDMA 34 58 /* 35 */ 59 #define TEGRA114_CLK_KBC 36 60 /* 37 */ 61 /* 38 */ 62 /* 39 (register bit affects fuse and fuse_burn) */ 63 #define TEGRA114_CLK_KFUSE 40 64 #define TEGRA114_CLK_SBC1 41 65 #define TEGRA114_CLK_NOR 42 66 /* 43 */ 67 #define TEGRA114_CLK_SBC2 44 68 /* 45 */ 69 #define TEGRA114_CLK_SBC3 46 70 #define TEGRA114_CLK_I2C5 47 71 #define TEGRA114_CLK_DSIA 48 72 /* 49 */ 73 #define TEGRA114_CLK_MIPI 50 74 #define TEGRA114_CLK_HDMI 51 75 #define TEGRA114_CLK_CSI 52 76 /* 53 */ 77 #define TEGRA114_CLK_I2C2 54 78 #define TEGRA114_CLK_UARTC 55 79 #define TEGRA114_CLK_MIPI_CAL 56 80 #define TEGRA114_CLK_EMC 57 81 #define TEGRA114_CLK_USB2 58 82 #define TEGRA114_CLK_USB3 59 83 /* 60 */ 84 #define TEGRA114_CLK_VDE 61 85 #define TEGRA114_CLK_BSEA 62 86 #define TEGRA114_CLK_BSEV 63 87 88 /* 64 */ 89 #define TEGRA114_CLK_UARTD 65 90 /* 66 */ 91 #define TEGRA114_CLK_I2C3 67 92 #define TEGRA114_CLK_SBC4 68 93 #define TEGRA114_CLK_SDMMC3 69 94 /* 70 */ 95 #define TEGRA114_CLK_OWR 71 96 /* 72 */ 97 #define TEGRA114_CLK_CSITE 73 98 /* 74 */ 99 /* 75 */ 100 #define TEGRA114_CLK_LA 76 101 #define TEGRA114_CLK_TRACE 77 102 #define TEGRA114_CLK_SOC_THERM 78 103 #define TEGRA114_CLK_DTV 79 104 #define TEGRA114_CLK_NDSPEED 80 105 #define TEGRA114_CLK_I2CSLOW 81 106 #define TEGRA114_CLK_DSIB 82 107 #define TEGRA114_CLK_TSEC 83 108 /* 84 */ 109 /* 85 */ 110 /* 86 */ 111 /* 87 */ 112 /* 88 */ 113 #define TEGRA114_CLK_XUSB_HOST 89 114 /* 90 */ 115 #define TEGRA114_CLK_MSENC 91 116 #define TEGRA114_CLK_CSUS 92 117 /* 93 */ 118 /* 94 */ 119 /* 95 (bit affects xusb_dev and xusb_dev_src) */ 120 121 /* 96 */ 122 /* 97 */ 123 /* 98 */ 124 #define TEGRA114_CLK_MSELECT 99 125 #define TEGRA114_CLK_TSENSOR 100 126 #define TEGRA114_CLK_I2S3 101 127 #define TEGRA114_CLK_I2S4 102 128 #define TEGRA114_CLK_I2C4 103 129 #define TEGRA114_CLK_SBC5 104 130 #define TEGRA114_CLK_SBC6 105 131 #define TEGRA114_CLK_D_AUDIO 106 132 #define TEGRA114_CLK_APBIF 107 133 #define TEGRA114_CLK_DAM0 108 134 #define TEGRA114_CLK_DAM1 109 135 #define TEGRA114_CLK_DAM2 110 136 #define TEGRA114_CLK_HDA2CODEC_2X 111 137 /* 112 */ 138 #define TEGRA114_CLK_AUDIO0_2X 113 139 #define TEGRA114_CLK_AUDIO1_2X 114 140 #define TEGRA114_CLK_AUDIO2_2X 115 141 #define TEGRA114_CLK_AUDIO3_2X 116 142 #define TEGRA114_CLK_AUDIO4_2X 117 143 #define TEGRA114_CLK_SPDIF_2X 118 144 #define TEGRA114_CLK_ACTMON 119 145 #define TEGRA114_CLK_EXTERN1 120 146 #define TEGRA114_CLK_EXTERN2 121 147 #define TEGRA114_CLK_EXTERN3 122 148 /* 123 */ 149 /* 124 */ 150 #define TEGRA114_CLK_HDA 125 151 /* 126 */ 152 #define TEGRA114_CLK_SE 127 153 154 #define TEGRA114_CLK_HDA2HDMI 128 155 /* 129 */ 156 /* 130 */ 157 /* 131 */ 158 /* 132 */ 159 /* 133 */ 160 /* 134 */ 161 /* 135 */ 162 #define TEGRA114_CLK_CEC 136 163 /* 137 */ 164 /* 138 */ 165 /* 139 */ 166 /* 140 */ 167 /* 141 */ 168 /* 142 */ 169 /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 170 /* xusb_host_src and xusb_ss_src) */ 171 #define TEGRA114_CLK_CILAB 144 172 #define TEGRA114_CLK_CILCD 145 173 #define TEGRA114_CLK_CILE 146 174 #define TEGRA114_CLK_DSIALP 147 175 #define TEGRA114_CLK_DSIBLP 148 176 /* 149 */ 177 #define TEGRA114_CLK_DDS 150 178 /* 151 */ 179 #define TEGRA114_CLK_DP2 152 180 #define TEGRA114_CLK_AMX 153 181 #define TEGRA114_CLK_ADX 154 182 /* 155 (bit affects dfll_ref and dfll_soc) */ 183 #define TEGRA114_CLK_XUSB_SS 156 184 /* 157 */ 185 /* 158 */ 186 /* 159 */ 187 188 /* 160 */ 189 /* 161 */ 190 /* 162 */ 191 /* 163 */ 192 /* 164 */ 193 /* 165 */ 194 /* 166 */ 195 /* 167 */ 196 /* 168 */ 197 /* 169 */ 198 /* 170 */ 199 /* 171 */ 200 /* 172 */ 201 /* 173 */ 202 /* 174 */ 203 /* 175 */ 204 /* 176 */ 205 /* 177 */ 206 /* 178 */ 207 /* 179 */ 208 /* 180 */ 209 /* 181 */ 210 /* 182 */ 211 /* 183 */ 212 /* 184 */ 213 /* 185 */ 214 /* 186 */ 215 /* 187 */ 216 /* 188 */ 217 /* 189 */ 218 /* 190 */ 219 /* 191 */ 220 221 #define TEGRA114_CLK_UARTB 192 222 #define TEGRA114_CLK_VFIR 193 223 #define TEGRA114_CLK_SPDIF_IN 194 224 #define TEGRA114_CLK_SPDIF_OUT 195 225 #define TEGRA114_CLK_VI 196 226 #define TEGRA114_CLK_VI_SENSOR 197 227 #define TEGRA114_CLK_FUSE 198 228 #define TEGRA114_CLK_FUSE_BURN 199 229 #define TEGRA114_CLK_CLK_32K 200 230 #define TEGRA114_CLK_CLK_M 201 231 #define TEGRA114_CLK_CLK_M_DIV2 202 232 #define TEGRA114_CLK_CLK_M_DIV4 203 233 #define TEGRA114_CLK_OSC_DIV2 202 234 #define TEGRA114_CLK_OSC_DIV4 203 235 #define TEGRA114_CLK_PLL_REF 204 236 #define TEGRA114_CLK_PLL_C 205 237 #define TEGRA114_CLK_PLL_C_OUT1 206 238 #define TEGRA114_CLK_PLL_C2 207 239 #define TEGRA114_CLK_PLL_C3 208 240 #define TEGRA114_CLK_PLL_M 209 241 #define TEGRA114_CLK_PLL_M_OUT1 210 242 #define TEGRA114_CLK_PLL_P 211 243 #define TEGRA114_CLK_PLL_P_OUT1 212 244 #define TEGRA114_CLK_PLL_P_OUT2 213 245 #define TEGRA114_CLK_PLL_P_OUT3 214 246 #define TEGRA114_CLK_PLL_P_OUT4 215 247 #define TEGRA114_CLK_PLL_A 216 248 #define TEGRA114_CLK_PLL_A_OUT0 217 249 #define TEGRA114_CLK_PLL_D 218 250 #define TEGRA114_CLK_PLL_D_OUT0 219 251 #define TEGRA114_CLK_PLL_D2 220 252 #define TEGRA114_CLK_PLL_D2_OUT0 221 253 #define TEGRA114_CLK_PLL_U 222 254 #define TEGRA114_CLK_PLL_U_480M 223 255 256 #define TEGRA114_CLK_PLL_U_60M 224 257 #define TEGRA114_CLK_PLL_U_48M 225 258 #define TEGRA114_CLK_PLL_U_12M 226 259 #define TEGRA114_CLK_PLL_X 227 260 #define TEGRA114_CLK_PLL_X_OUT0 228 261 #define TEGRA114_CLK_PLL_RE_VCO 229 262 #define TEGRA114_CLK_PLL_RE_OUT 230 263 #define TEGRA114_CLK_PLL_E_OUT0 231 264 #define TEGRA114_CLK_SPDIF_IN_SYNC 232 265 #define TEGRA114_CLK_I2S0_SYNC 233 266 #define TEGRA114_CLK_I2S1_SYNC 234 267 #define TEGRA114_CLK_I2S2_SYNC 235 268 #define TEGRA114_CLK_I2S3_SYNC 236 269 #define TEGRA114_CLK_I2S4_SYNC 237 270 #define TEGRA114_CLK_VIMCLK_SYNC 238 271 #define TEGRA114_CLK_AUDIO0 239 272 #define TEGRA114_CLK_AUDIO1 240 273 #define TEGRA114_CLK_AUDIO2 241 274 #define TEGRA114_CLK_AUDIO3 242 275 #define TEGRA114_CLK_AUDIO4 243 276 #define TEGRA114_CLK_SPDIF 244 277 /* 245 */ 278 /* 246 */ 279 /* 247 */ 280 /* 248 */ 281 #define TEGRA114_CLK_OSC 249 282 /* 250 */ 283 /* 251 */ 284 #define TEGRA114_CLK_XUSB_HOST_SRC 252 285 #define TEGRA114_CLK_XUSB_FALCON_SRC 253 286 #define TEGRA114_CLK_XUSB_FS_SRC 254 287 #define TEGRA114_CLK_XUSB_SS_SRC 255 288 289 #define TEGRA114_CLK_XUSB_DEV_SRC 256 290 #define TEGRA114_CLK_XUSB_DEV 257 291 #define TEGRA114_CLK_XUSB_HS_SRC 258 292 #define TEGRA114_CLK_SCLK 259 293 #define TEGRA114_CLK_HCLK 260 294 #define TEGRA114_CLK_PCLK 261 295 #define TEGRA114_CLK_CCLK_G 262 296 #define TEGRA114_CLK_CCLK_LP 263 297 #define TEGRA114_CLK_DFLL_REF 264 298 #define TEGRA114_CLK_DFLL_SOC 265 299 /* 266 */ 300 /* 267 */ 301 /* 268 */ 302 /* 269 */ 303 /* 270 */ 304 /* 271 */ 305 /* 272 */ 306 /* 273 */ 307 /* 274 */ 308 /* 275 */ 309 /* 276 */ 310 /* 277 */ 311 /* 278 */ 312 /* 279 */ 313 /* 280 */ 314 /* 281 */ 315 /* 282 */ 316 /* 283 */ 317 /* 284 */ 318 /* 285 */ 319 /* 286 */ 320 /* 287 */ 321 322 /* 288 */ 323 /* 289 */ 324 /* 290 */ 325 /* 291 */ 326 /* 292 */ 327 /* 293 */ 328 /* 294 */ 329 /* 295 */ 330 /* 296 */ 331 /* 297 */ 332 /* 298 */ 333 /* 299 */ 334 #define TEGRA114_CLK_AUDIO0_MUX 300 335 #define TEGRA114_CLK_AUDIO1_MUX 301 336 #define TEGRA114_CLK_AUDIO2_MUX 302 337 #define TEGRA114_CLK_AUDIO3_MUX 303 338 #define TEGRA114_CLK_AUDIO4_MUX 304 339 #define TEGRA114_CLK_SPDIF_MUX 305 340 /* 306 */ 341 /* 307 */ 342 /* 308 */ 343 #define TEGRA114_CLK_DSIA_MUX 309 344 #define TEGRA114_CLK_DSIB_MUX 310 345 #define TEGRA114_CLK_XUSB_SS_DIV2 311 346 #define TEGRA114_CLK_CLK_MAX 312 347 348 #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */ 349
Indexes created Tue Sep 30 20:09:53 GMT 2025