1 /* $NetBSD: tegra124-car-common.h,v 1.1.1.5 2021/11/07 16:49:58 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * This header provides constants for binding nvidia,tegra124-car or 6 * nvidia,tegra132-car. 7 * 8 * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 9 * registers. These IDs often match those in the CAR's RST_DEVICES registers, 10 * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 11 * this case, those clocks are assigned IDs above 185 in order to highlight 12 * this issue. Implementations that interpret these clock IDs as bit values 13 * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 14 * explicitly handle these special cases. 15 * 16 * The balance of the clocks controlled by the CAR are assigned IDs of 185 and 17 * above. 18 */ 19 20 #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 21 #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H 22 23 /* 0 */ 24 /* 1 */ 25 /* 2 */ 26 #define TEGRA124_CLK_ISPB 3 27 #define TEGRA124_CLK_RTC 4 28 #define TEGRA124_CLK_TIMER 5 29 #define TEGRA124_CLK_UARTA 6 30 /* 7 (register bit affects uartb and vfir) */ 31 /* 8 */ 32 #define TEGRA124_CLK_SDMMC2 9 33 /* 10 (register bit affects spdif_in and spdif_out) */ 34 #define TEGRA124_CLK_I2S1 11 35 #define TEGRA124_CLK_I2C1 12 36 /* 13 */ 37 #define TEGRA124_CLK_SDMMC1 14 38 #define TEGRA124_CLK_SDMMC4 15 39 /* 16 */ 40 #define TEGRA124_CLK_PWM 17 41 #define TEGRA124_CLK_I2S2 18 42 /* 20 (register bit affects vi and vi_sensor) */ 43 /* 21 */ 44 #define TEGRA124_CLK_USBD 22 45 #define TEGRA124_CLK_ISP 23 46 /* 26 */ 47 /* 25 */ 48 #define TEGRA124_CLK_DISP2 26 49 #define TEGRA124_CLK_DISP1 27 50 #define TEGRA124_CLK_HOST1X 28 51 #define TEGRA124_CLK_VCP 29 52 #define TEGRA124_CLK_I2S0 30 53 /* 31 */ 54 55 #define TEGRA124_CLK_MC 32 56 /* 33 */ 57 #define TEGRA124_CLK_APBDMA 34 58 /* 35 */ 59 #define TEGRA124_CLK_KBC 36 60 /* 37 */ 61 /* 38 */ 62 /* 39 (register bit affects fuse and fuse_burn) */ 63 #define TEGRA124_CLK_KFUSE 40 64 #define TEGRA124_CLK_SBC1 41 65 #define TEGRA124_CLK_NOR 42 66 /* 43 */ 67 #define TEGRA124_CLK_SBC2 44 68 /* 45 */ 69 #define TEGRA124_CLK_SBC3 46 70 #define TEGRA124_CLK_I2C5 47 71 #define TEGRA124_CLK_DSIA 48 72 /* 49 */ 73 #define TEGRA124_CLK_MIPI 50 74 #define TEGRA124_CLK_HDMI 51 75 #define TEGRA124_CLK_CSI 52 76 /* 53 */ 77 #define TEGRA124_CLK_I2C2 54 78 #define TEGRA124_CLK_UARTC 55 79 #define TEGRA124_CLK_MIPI_CAL 56 80 #define TEGRA124_CLK_EMC 57 81 #define TEGRA124_CLK_USB2 58 82 #define TEGRA124_CLK_USB3 59 83 /* 60 */ 84 #define TEGRA124_CLK_VDE 61 85 #define TEGRA124_CLK_BSEA 62 86 #define TEGRA124_CLK_BSEV 63 87 88 /* 64 */ 89 #define TEGRA124_CLK_UARTD 65 90 /* 66 */ 91 #define TEGRA124_CLK_I2C3 67 92 #define TEGRA124_CLK_SBC4 68 93 #define TEGRA124_CLK_SDMMC3 69 94 #define TEGRA124_CLK_PCIE 70 95 #define TEGRA124_CLK_OWR 71 96 #define TEGRA124_CLK_AFI 72 97 #define TEGRA124_CLK_CSITE 73 98 /* 74 */ 99 /* 75 */ 100 #define TEGRA124_CLK_LA 76 101 #define TEGRA124_CLK_TRACE 77 102 #define TEGRA124_CLK_SOC_THERM 78 103 #define TEGRA124_CLK_DTV 79 104 /* 80 */ 105 #define TEGRA124_CLK_I2CSLOW 81 106 #define TEGRA124_CLK_DSIB 82 107 #define TEGRA124_CLK_TSEC 83 108 /* 84 */ 109 /* 85 */ 110 /* 86 */ 111 /* 87 */ 112 /* 88 */ 113 #define TEGRA124_CLK_XUSB_HOST 89 114 /* 90 */ 115 #define TEGRA124_CLK_MSENC 91 116 #define TEGRA124_CLK_CSUS 92 117 /* 93 */ 118 /* 94 */ 119 /* 95 (bit affects xusb_dev and xusb_dev_src) */ 120 121 /* 96 */ 122 /* 97 */ 123 /* 98 */ 124 #define TEGRA124_CLK_MSELECT 99 125 #define TEGRA124_CLK_TSENSOR 100 126 #define TEGRA124_CLK_I2S3 101 127 #define TEGRA124_CLK_I2S4 102 128 #define TEGRA124_CLK_I2C4 103 129 #define TEGRA124_CLK_SBC5 104 130 #define TEGRA124_CLK_SBC6 105 131 #define TEGRA124_CLK_D_AUDIO 106 132 #define TEGRA124_CLK_APBIF 107 133 #define TEGRA124_CLK_DAM0 108 134 #define TEGRA124_CLK_DAM1 109 135 #define TEGRA124_CLK_DAM2 110 136 #define TEGRA124_CLK_HDA2CODEC_2X 111 137 /* 112 */ 138 #define TEGRA124_CLK_AUDIO0_2X 113 139 #define TEGRA124_CLK_AUDIO1_2X 114 140 #define TEGRA124_CLK_AUDIO2_2X 115 141 #define TEGRA124_CLK_AUDIO3_2X 116 142 #define TEGRA124_CLK_AUDIO4_2X 117 143 #define TEGRA124_CLK_SPDIF_2X 118 144 #define TEGRA124_CLK_ACTMON 119 145 #define TEGRA124_CLK_EXTERN1 120 146 #define TEGRA124_CLK_EXTERN2 121 147 #define TEGRA124_CLK_EXTERN3 122 148 #define TEGRA124_CLK_SATA_OOB 123 149 #define TEGRA124_CLK_SATA 124 150 #define TEGRA124_CLK_HDA 125 151 /* 126 */ 152 #define TEGRA124_CLK_SE 127 153 154 #define TEGRA124_CLK_HDA2HDMI 128 155 #define TEGRA124_CLK_SATA_COLD 129 156 /* 130 */ 157 /* 131 */ 158 /* 132 */ 159 /* 133 */ 160 /* 134 */ 161 /* 135 */ 162 #define TEGRA124_CLK_CEC 136 163 /* 137 */ 164 /* 138 */ 165 /* 139 */ 166 /* 140 */ 167 /* 141 */ 168 /* 142 */ 169 /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */ 170 /* xusb_host_src and xusb_ss_src) */ 171 #define TEGRA124_CLK_CILAB 144 172 #define TEGRA124_CLK_CILCD 145 173 #define TEGRA124_CLK_CILE 146 174 #define TEGRA124_CLK_DSIALP 147 175 #define TEGRA124_CLK_DSIBLP 148 176 #define TEGRA124_CLK_ENTROPY 149 177 #define TEGRA124_CLK_DDS 150 178 /* 151 */ 179 #define TEGRA124_CLK_DP2 152 180 #define TEGRA124_CLK_AMX 153 181 #define TEGRA124_CLK_ADX 154 182 /* 155 (bit affects dfll_ref and dfll_soc) */ 183 #define TEGRA124_CLK_XUSB_SS 156 184 /* 157 */ 185 /* 158 */ 186 /* 159 */ 187 188 /* 160 */ 189 /* 161 */ 190 /* 162 */ 191 /* 163 */ 192 /* 164 */ 193 /* 165 */ 194 #define TEGRA124_CLK_I2C6 166 195 /* 167 */ 196 /* 168 */ 197 /* 169 */ 198 /* 170 */ 199 #define TEGRA124_CLK_VIM2_CLK 171 200 /* 172 */ 201 /* 173 */ 202 /* 174 */ 203 /* 175 */ 204 #define TEGRA124_CLK_HDMI_AUDIO 176 205 #define TEGRA124_CLK_CLK72MHZ 177 206 #define TEGRA124_CLK_VIC03 178 207 /* 179 */ 208 #define TEGRA124_CLK_ADX1 180 209 #define TEGRA124_CLK_DPAUX 181 210 #define TEGRA124_CLK_SOR0 182 211 /* 183 */ 212 #define TEGRA124_CLK_GPU 184 213 #define TEGRA124_CLK_AMX1 185 214 /* 186 */ 215 /* 187 */ 216 /* 188 */ 217 /* 189 */ 218 /* 190 */ 219 /* 191 */ 220 #define TEGRA124_CLK_UARTB 192 221 #define TEGRA124_CLK_VFIR 193 222 #define TEGRA124_CLK_SPDIF_IN 194 223 #define TEGRA124_CLK_SPDIF_OUT 195 224 #define TEGRA124_CLK_VI 196 225 #define TEGRA124_CLK_VI_SENSOR 197 226 #define TEGRA124_CLK_FUSE 198 227 #define TEGRA124_CLK_FUSE_BURN 199 228 #define TEGRA124_CLK_CLK_32K 200 229 #define TEGRA124_CLK_CLK_M 201 230 #define TEGRA124_CLK_CLK_M_DIV2 202 231 #define TEGRA124_CLK_CLK_M_DIV4 203 232 #define TEGRA124_CLK_OSC_DIV2 202 233 #define TEGRA124_CLK_OSC_DIV4 203 234 #define TEGRA124_CLK_PLL_REF 204 235 #define TEGRA124_CLK_PLL_C 205 236 #define TEGRA124_CLK_PLL_C_OUT1 206 237 #define TEGRA124_CLK_PLL_C2 207 238 #define TEGRA124_CLK_PLL_C3 208 239 #define TEGRA124_CLK_PLL_M 209 240 #define TEGRA124_CLK_PLL_M_OUT1 210 241 #define TEGRA124_CLK_PLL_P 211 242 #define TEGRA124_CLK_PLL_P_OUT1 212 243 #define TEGRA124_CLK_PLL_P_OUT2 213 244 #define TEGRA124_CLK_PLL_P_OUT3 214 245 #define TEGRA124_CLK_PLL_P_OUT4 215 246 #define TEGRA124_CLK_PLL_A 216 247 #define TEGRA124_CLK_PLL_A_OUT0 217 248 #define TEGRA124_CLK_PLL_D 218 249 #define TEGRA124_CLK_PLL_D_OUT0 219 250 #define TEGRA124_CLK_PLL_D2 220 251 #define TEGRA124_CLK_PLL_D2_OUT0 221 252 #define TEGRA124_CLK_PLL_U 222 253 #define TEGRA124_CLK_PLL_U_480M 223 254 255 #define TEGRA124_CLK_PLL_U_60M 224 256 #define TEGRA124_CLK_PLL_U_48M 225 257 #define TEGRA124_CLK_PLL_U_12M 226 258 /* 227 */ 259 /* 228 */ 260 #define TEGRA124_CLK_PLL_RE_VCO 229 261 #define TEGRA124_CLK_PLL_RE_OUT 230 262 #define TEGRA124_CLK_PLL_E 231 263 #define TEGRA124_CLK_SPDIF_IN_SYNC 232 264 #define TEGRA124_CLK_I2S0_SYNC 233 265 #define TEGRA124_CLK_I2S1_SYNC 234 266 #define TEGRA124_CLK_I2S2_SYNC 235 267 #define TEGRA124_CLK_I2S3_SYNC 236 268 #define TEGRA124_CLK_I2S4_SYNC 237 269 #define TEGRA124_CLK_VIMCLK_SYNC 238 270 #define TEGRA124_CLK_AUDIO0 239 271 #define TEGRA124_CLK_AUDIO1 240 272 #define TEGRA124_CLK_AUDIO2 241 273 #define TEGRA124_CLK_AUDIO3 242 274 #define TEGRA124_CLK_AUDIO4 243 275 #define TEGRA124_CLK_SPDIF 244 276 /* 245 */ 277 /* 246 */ 278 /* 247 */ 279 /* 248 */ 280 #define TEGRA124_CLK_OSC 249 281 /* 250 */ 282 /* 251 */ 283 #define TEGRA124_CLK_XUSB_HOST_SRC 252 284 #define TEGRA124_CLK_XUSB_FALCON_SRC 253 285 #define TEGRA124_CLK_XUSB_FS_SRC 254 286 #define TEGRA124_CLK_XUSB_SS_SRC 255 287 288 #define TEGRA124_CLK_XUSB_DEV_SRC 256 289 #define TEGRA124_CLK_XUSB_DEV 257 290 #define TEGRA124_CLK_XUSB_HS_SRC 258 291 #define TEGRA124_CLK_SCLK 259 292 #define TEGRA124_CLK_HCLK 260 293 #define TEGRA124_CLK_PCLK 261 294 /* 262 */ 295 /* 263 */ 296 #define TEGRA124_CLK_DFLL_REF 264 297 #define TEGRA124_CLK_DFLL_SOC 265 298 #define TEGRA124_CLK_VI_SENSOR2 266 299 #define TEGRA124_CLK_PLL_P_OUT5 267 300 #define TEGRA124_CLK_CML0 268 301 #define TEGRA124_CLK_CML1 269 302 #define TEGRA124_CLK_PLL_C4 270 303 #define TEGRA124_CLK_PLL_DP 271 304 #define TEGRA124_CLK_PLL_E_MUX 272 305 #define TEGRA124_CLK_PLL_D_DSI_OUT 273 306 /* 274 */ 307 /* 275 */ 308 /* 276 */ 309 /* 277 */ 310 /* 278 */ 311 /* 279 */ 312 /* 280 */ 313 /* 281 */ 314 /* 282 */ 315 /* 283 */ 316 /* 284 */ 317 /* 285 */ 318 /* 286 */ 319 /* 287 */ 320 321 /* 288 */ 322 /* 289 */ 323 /* 290 */ 324 /* 291 */ 325 /* 292 */ 326 /* 293 */ 327 /* 294 */ 328 /* 295 */ 329 /* 296 */ 330 /* 297 */ 331 /* 298 */ 332 /* 299 */ 333 #define TEGRA124_CLK_AUDIO0_MUX 300 334 #define TEGRA124_CLK_AUDIO1_MUX 301 335 #define TEGRA124_CLK_AUDIO2_MUX 302 336 #define TEGRA124_CLK_AUDIO3_MUX 303 337 #define TEGRA124_CLK_AUDIO4_MUX 304 338 #define TEGRA124_CLK_SPDIF_MUX 305 339 /* 306 */ 340 /* 307 */ 341 /* 308 */ 342 /* 309 */ 343 /* 310 */ 344 #define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */ 345 #define TEGRA124_CLK_SOR0_OUT 311 346 #define TEGRA124_CLK_XUSB_SS_DIV2 312 347 348 #define TEGRA124_CLK_PLL_M_UD 313 349 #define TEGRA124_CLK_PLL_C_UD 314 350 351 #endif /* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */ 352
Indexes created Wed Oct 01 19:09:53 GMT 2025