1/*	$NetBSD: thead,th1520-clk-ap.h,v 1.1.1.1 2026/01/18 05:21:43 skrll Exp $	*/
2
3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
4/*
5 * Copyright (C) 2023 Vivo Communication Technology Co. Ltd.
6 * Authors: Yangtao Li <frank.li@vivo.com>
7 */
8
9#ifndef _DT_BINDINGS_CLK_TH1520_H_
10#define _DT_BINDINGS_CLK_TH1520_H_
11
12#define CLK_CPU_PLL0		0
13#define CLK_CPU_PLL1		1
14#define CLK_GMAC_PLL		2
15#define CLK_VIDEO_PLL		3
16#define CLK_DPU0_PLL		4
17#define CLK_DPU1_PLL		5
18#define CLK_TEE_PLL		6
19#define CLK_C910_I0		7
20#define CLK_C910		8
21#define CLK_BROM		9
22#define CLK_BMU			10
23#define CLK_AHB2_CPUSYS_HCLK	11
24#define CLK_APB3_CPUSYS_PCLK	12
25#define CLK_AXI4_CPUSYS2_ACLK	13
26#define CLK_AON2CPU_A2X		14
27#define CLK_X2X_CPUSYS		15
28#define CLK_AXI_ACLK		16
29#define CLK_CPU2AON_X2H		17
30#define CLK_PERI_AHB_HCLK	18
31#define CLK_CPU2PERI_X2H	19
32#define CLK_PERI_APB_PCLK	20
33#define CLK_PERI2APB_PCLK	21
34#define CLK_PERISYS_APB1_HCLK	22
35#define CLK_PERISYS_APB2_HCLK	23
36#define CLK_PERISYS_APB3_HCLK	24
37#define CLK_PERISYS_APB4_HCLK	25
38#define CLK_OSC12M		26
39#define CLK_OUT1		27
40#define CLK_OUT2		28
41#define CLK_OUT3		29
42#define CLK_OUT4		30
43#define CLK_APB_PCLK		31
44#define CLK_NPU			32
45#define CLK_NPU_AXI		33
46#define CLK_VI			34
47#define CLK_VI_AHB		35
48#define CLK_VO_AXI		36
49#define CLK_VP_APB		37
50#define CLK_VP_AXI		38
51#define CLK_CPU2VP		39
52#define CLK_VENC		40
53#define CLK_DPU0		41
54#define CLK_DPU1		42
55#define CLK_EMMC_SDIO		43
56#define CLK_GMAC1		44
57#define CLK_PADCTRL1		45
58#define CLK_DSMART		46
59#define CLK_PADCTRL0		47
60#define CLK_GMAC_AXI		48
61#define CLK_GPIO3		49
62#define CLK_GMAC0		50
63#define CLK_PWM			51
64#define CLK_QSPI0		52
65#define CLK_QSPI1		53
66#define CLK_SPI			54
67#define CLK_UART0_PCLK		55
68#define CLK_UART1_PCLK		56
69#define CLK_UART2_PCLK		57
70#define CLK_UART3_PCLK		58
71#define CLK_UART4_PCLK		59
72#define CLK_UART5_PCLK		60
73#define CLK_GPIO0		61
74#define CLK_GPIO1		62
75#define CLK_GPIO2		63
76#define CLK_I2C0		64
77#define CLK_I2C1		65
78#define CLK_I2C2		66
79#define CLK_I2C3		67
80#define CLK_I2C4		68
81#define CLK_I2C5		69
82#define CLK_SPINLOCK		70
83#define CLK_DMA			71
84#define CLK_MBOX0		72
85#define CLK_MBOX1		73
86#define CLK_MBOX2		74
87#define CLK_MBOX3		75
88#define CLK_WDT0		76
89#define CLK_WDT1		77
90#define CLK_TIMER0		78
91#define CLK_TIMER1		79
92#define CLK_SRAM0		80
93#define CLK_SRAM1		81
94#define CLK_SRAM2		82
95#define CLK_SRAM3		83
96#define CLK_PLL_GMAC_100M	84
97#define CLK_UART_SCLK		85
98#endif
99