1 1.1 jmcneill /* $NetBSD: x1830-dma.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 1.1 jmcneill 3 1.1 jmcneill /* SPDX-License-Identifier: GPL-2.0-only */ 4 1.1 jmcneill /* 5 1.1 jmcneill * This header provides macros for X1830 DMA bindings. 6 1.1 jmcneill * 7 1.1 jmcneill * Copyright (c) 2019 (Zhou Yanjie) <zhouyanjie (at) wanyeetech.com> 8 1.1 jmcneill */ 9 1.1 jmcneill 10 1.1 jmcneill #ifndef __DT_BINDINGS_DMA_X1830_DMA_H__ 11 1.1 jmcneill #define __DT_BINDINGS_DMA_X1830_DMA_H__ 12 1.1 jmcneill 13 1.1 jmcneill /* 14 1.1 jmcneill * Request type numbers for the X1830 DMA controller (written to the DRTn 15 1.1 jmcneill * register for the channel). 16 1.1 jmcneill */ 17 1.1 jmcneill #define X1830_DMA_I2S0_TX 0x6 18 1.1 jmcneill #define X1830_DMA_I2S0_RX 0x7 19 1.1 jmcneill #define X1830_DMA_AUTO 0x8 20 1.1 jmcneill #define X1830_DMA_SADC_RX 0x9 21 1.1 jmcneill #define X1830_DMA_UART1_TX 0x12 22 1.1 jmcneill #define X1830_DMA_UART1_RX 0x13 23 1.1 jmcneill #define X1830_DMA_UART0_TX 0x14 24 1.1 jmcneill #define X1830_DMA_UART0_RX 0x15 25 1.1 jmcneill #define X1830_DMA_SSI0_TX 0x16 26 1.1 jmcneill #define X1830_DMA_SSI0_RX 0x17 27 1.1 jmcneill #define X1830_DMA_SSI1_TX 0x18 28 1.1 jmcneill #define X1830_DMA_SSI1_RX 0x19 29 1.1 jmcneill #define X1830_DMA_MSC0_TX 0x1a 30 1.1 jmcneill #define X1830_DMA_MSC0_RX 0x1b 31 1.1 jmcneill #define X1830_DMA_MSC1_TX 0x1c 32 1.1 jmcneill #define X1830_DMA_MSC1_RX 0x1d 33 1.1 jmcneill #define X1830_DMA_DMIC_RX 0x21 34 1.1 jmcneill #define X1830_DMA_SMB0_TX 0x24 35 1.1 jmcneill #define X1830_DMA_SMB0_RX 0x25 36 1.1 jmcneill #define X1830_DMA_SMB1_TX 0x26 37 1.1 jmcneill #define X1830_DMA_SMB1_RX 0x27 38 1.1 jmcneill #define X1830_DMA_DES_TX 0x2e 39 1.1 jmcneill #define X1830_DMA_DES_RX 0x2f 40 1.1 jmcneill 41 1.1 jmcneill #endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */ 42
Indexes created Tue Sep 30 17:09:57 GMT 2025