Home | History | Annotate | Line # | Download | only in gce 
      1 /*	$NetBSD: mediatek,mt6795-gce.h,v 1.1.1.1 2026/01/18 05:21:43 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
      4 /*
      5  * Copyright (c) 2023 Collabora Ltd.
      6  * Author: AngeloGioacchino Del Regno <angelogioacchino.delregno (at) collabora.com>
      7  */
      8 #ifndef _DT_BINDINGS_GCE_MT6795_H
      9 #define _DT_BINDINGS_GCE_MT6795_H
     10 
     11 /* GCE HW thread priority */
     12 #define CMDQ_THR_PRIO_LOWEST			0
     13 #define CMDQ_THR_PRIO_NORMAL			1
     14 #define CMDQ_THR_PRIO_NORMAL_2			2
     15 #define CMDQ_THR_PRIO_MEDIUM			3
     16 #define CMDQ_THR_PRIO_MEDIUM_2			4
     17 #define CMDQ_THR_PRIO_HIGH			5
     18 #define CMDQ_THR_PRIO_HIGHER			6
     19 #define CMDQ_THR_PRIO_HIGHEST			7
     20 
     21 /* GCE SUBSYS */
     22 #define SUBSYS_1300XXXX				0
     23 #define SUBSYS_1400XXXX				1
     24 #define SUBSYS_1401XXXX				2
     25 #define SUBSYS_1402XXXX				3
     26 #define SUBSYS_1500XXXX				4
     27 #define SUBSYS_1600XXXX				5
     28 #define SUBSYS_1700XXXX				6
     29 #define SUBSYS_1800XXXX				7
     30 #define SUBSYS_1000XXXX				8
     31 #define SUBSYS_1001XXXX				9
     32 #define SUBSYS_1002XXXX				10
     33 #define SUBSYS_1003XXXX				11
     34 #define SUBSYS_1004XXXX				12
     35 #define SUBSYS_1005XXXX				13
     36 #define SUBSYS_1020XXXX				14
     37 #define SUBSYS_1021XXXX				15
     38 #define SUBSYS_1120XXXX				16
     39 #define SUBSYS_1121XXXX				17
     40 #define SUBSYS_1122XXXX				18
     41 #define SUBSYS_1123XXXX				19
     42 #define SUBSYS_1124XXXX				20
     43 #define SUBSYS_1125XXXX				21
     44 #define SUBSYS_1126XXXX				22
     45 
     46 /* GCE HW EVENT */
     47 #define CMDQ_EVENT_MDP_RDMA0_SOF		0
     48 #define CMDQ_EVENT_MDP_RDMA1_SOF		1
     49 #define CMDQ_EVENT_MDP_DSI0_TE_SOF		2
     50 #define CMDQ_EVENT_MDP_DSI1_TE_SOF		3
     51 #define CMDQ_EVENT_MDP_MVW_SOF			4
     52 #define CMDQ_EVENT_MDP_TDSHP0_SOF		5
     53 #define CMDQ_EVENT_MDP_TDSHP1_SOF		6
     54 #define CMDQ_EVENT_MDP_WDMA_SOF			7
     55 #define CMDQ_EVENT_MDP_WROT0_SOF		8
     56 #define CMDQ_EVENT_MDP_WROT1_SOF		9
     57 #define CMDQ_EVENT_MDP_CROP_SOF			10
     58 #define CMDQ_EVENT_DISP_OVL0_SOF		11
     59 #define CMDQ_EVENT_DISP_OVL1_SOF		12
     60 #define CMDQ_EVENT_DISP_RDMA0_SOF		13
     61 #define CMDQ_EVENT_DISP_RDMA1_SOF		14
     62 #define CMDQ_EVENT_DISP_RDMA2_SOF		15
     63 #define CMDQ_EVENT_DISP_WDMA0_SOF		16
     64 #define CMDQ_EVENT_DISP_WDMA1_SOF		17
     65 #define CMDQ_EVENT_DISP_COLOR0_SOF		18
     66 #define CMDQ_EVENT_DISP_COLOR1_SOF		19
     67 #define CMDQ_EVENT_DISP_AAL_SOF			20
     68 #define CMDQ_EVENT_DISP_GAMMA_SOF		21
     69 #define CMDQ_EVENT_DISP_UFOE_SOF		22
     70 #define CMDQ_EVENT_DISP_PWM0_SOF		23
     71 #define CMDQ_EVENT_DISP_PWM1_SOF		24
     72 #define CMDQ_EVENT_DISP_OD_SOF			25
     73 #define CMDQ_EVENT_MDP_RDMA0_EOF		26
     74 #define CMDQ_EVENT_MDP_RDMA1_EOF		27
     75 #define CMDQ_EVENT_MDP_RSZ0_EOF			28
     76 #define CMDQ_EVENT_MDP_RSZ1_EOF			29
     77 #define CMDQ_EVENT_MDP_RSZ2_EOF			30
     78 #define CMDQ_EVENT_MDP_TDSHP0_EOF		31
     79 #define CMDQ_EVENT_MDP_TDSHP1_EOF		32
     80 #define CMDQ_EVENT_MDP_WDMA_EOF			33
     81 #define CMDQ_EVENT_MDP_WROT0_WRITE_EOF		34
     82 #define CMDQ_EVENT_MDP_WROT0_READ_EOF		35
     83 #define CMDQ_EVENT_MDP_WROT1_WRITE_EOF		36
     84 #define CMDQ_EVENT_MDP_WROT1_READ_EOF		37
     85 #define CMDQ_EVENT_MDP_CROP_EOF			38
     86 #define CMDQ_EVENT_DISP_OVL0_EOF		39
     87 #define CMDQ_EVENT_DISP_OVL1_EOF		40
     88 #define CMDQ_EVENT_DISP_RDMA0_EOF		41
     89 #define CMDQ_EVENT_DISP_RDMA1_EOF		42
     90 #define CMDQ_EVENT_DISP_RDMA2_EOF		43
     91 #define CMDQ_EVENT_DISP_WDMA0_EOF		44
     92 #define CMDQ_EVENT_DISP_WDMA1_EOF		45
     93 #define CMDQ_EVENT_DISP_COLOR0_EOF		46
     94 #define CMDQ_EVENT_DISP_COLOR1_EOF		47
     95 #define CMDQ_EVENT_DISP_AAL_EOF			48
     96 #define CMDQ_EVENT_DISP_GAMMA_EOF		49
     97 #define CMDQ_EVENT_DISP_UFOE_EOF		50
     98 #define CMDQ_EVENT_DISP_DPI0_EOF		51
     99 #define CMDQ_EVENT_MUTEX0_STREAM_EOF		52
    100 #define CMDQ_EVENT_MUTEX1_STREAM_EOF		53
    101 #define CMDQ_EVENT_MUTEX2_STREAM_EOF		54
    102 #define CMDQ_EVENT_MUTEX3_STREAM_EOF		55
    103 #define CMDQ_EVENT_MUTEX4_STREAM_EOF		56
    104 #define CMDQ_EVENT_MUTEX5_STREAM_EOF		57
    105 #define CMDQ_EVENT_MUTEX6_STREAM_EOF		58
    106 #define CMDQ_EVENT_MUTEX7_STREAM_EOF		59
    107 #define CMDQ_EVENT_MUTEX8_STREAM_EOF		60
    108 #define CMDQ_EVENT_MUTEX9_STREAM_EOF		61
    109 #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN		62
    110 #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN		63
    111 #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN		64
    112 #define CMDQ_EVENT_ISP_PASS2_2_EOF		129
    113 #define CMDQ_EVENT_ISP_PASS2_1_EOF		130
    114 #define CMDQ_EVENT_ISP_PASS2_0_EOF		131
    115 #define CMDQ_EVENT_ISP_PASS1_1_EOF		132
    116 #define CMDQ_EVENT_ISP_PASS1_0_EOF		133
    117 #define CMDQ_EVENT_CAMSV_2_PASS1_EOF		134
    118 #define CMDQ_EVENT_CAMSV_1_PASS1_EOF		135
    119 #define CMDQ_EVENT_SENINF_CAM1_2_3_FIFO_FULL	136
    120 #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL	137
    121 #define CMDQ_EVENT_JPGENC_PASS2_EOF		257
    122 #define CMDQ_EVENT_JPGENC_PASS1_EOF		258
    123 #define CMDQ_EVENT_JPGDEC_EOF			259
    124 
    125 #endif
    126