1 /* $NetBSD: mt6779-gce.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2019 MediaTek Inc. 6 * Author: Dennis-YC Hsieh <dennis-yc.hsieh (at) mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_GCE_MT6779_H 10 #define _DT_BINDINGS_GCE_MT6779_H 11 12 #define CMDQ_NO_TIMEOUT 0xffffffff 13 14 /* GCE HW thread priority */ 15 #define CMDQ_THR_PRIO_LOWEST 0 16 #define CMDQ_THR_PRIO_1 1 17 #define CMDQ_THR_PRIO_2 2 18 #define CMDQ_THR_PRIO_3 3 19 #define CMDQ_THR_PRIO_4 4 20 #define CMDQ_THR_PRIO_5 5 21 #define CMDQ_THR_PRIO_6 6 22 #define CMDQ_THR_PRIO_HIGHEST 7 23 24 /* GCE subsys table */ 25 #define SUBSYS_1300XXXX 0 26 #define SUBSYS_1400XXXX 1 27 #define SUBSYS_1401XXXX 2 28 #define SUBSYS_1402XXXX 3 29 #define SUBSYS_1502XXXX 4 30 #define SUBSYS_1880XXXX 5 31 #define SUBSYS_1881XXXX 6 32 #define SUBSYS_1882XXXX 7 33 #define SUBSYS_1883XXXX 8 34 #define SUBSYS_1884XXXX 9 35 #define SUBSYS_1000XXXX 10 36 #define SUBSYS_1001XXXX 11 37 #define SUBSYS_1002XXXX 12 38 #define SUBSYS_1003XXXX 13 39 #define SUBSYS_1004XXXX 14 40 #define SUBSYS_1005XXXX 15 41 #define SUBSYS_1020XXXX 16 42 #define SUBSYS_1028XXXX 17 43 #define SUBSYS_1700XXXX 18 44 #define SUBSYS_1701XXXX 19 45 #define SUBSYS_1702XXXX 20 46 #define SUBSYS_1703XXXX 21 47 #define SUBSYS_1800XXXX 22 48 #define SUBSYS_1801XXXX 23 49 #define SUBSYS_1802XXXX 24 50 #define SUBSYS_1804XXXX 25 51 #define SUBSYS_1805XXXX 26 52 #define SUBSYS_1808XXXX 27 53 #define SUBSYS_180aXXXX 28 54 #define SUBSYS_180bXXXX 29 55 #define CMDQ_SUBSYS_OFF 32 56 57 /* GCE hardware events */ 58 #define CMDQ_EVENT_DISP_RDMA0_SOF 0 59 #define CMDQ_EVENT_DISP_RDMA1_SOF 1 60 #define CMDQ_EVENT_MDP_RDMA0_SOF 2 61 #define CMDQ_EVENT_MDP_RDMA1_SOF 3 62 #define CMDQ_EVENT_MDP_RSZ0_SOF 4 63 #define CMDQ_EVENT_MDP_RSZ1_SOF 5 64 #define CMDQ_EVENT_MDP_TDSHP_SOF 6 65 #define CMDQ_EVENT_MDP_WROT0_SOF 7 66 #define CMDQ_EVENT_MDP_WROT1_SOF 8 67 #define CMDQ_EVENT_DISP_OVL0_SOF 9 68 #define CMDQ_EVENT_DISP_2L_OVL0_SOF 10 69 #define CMDQ_EVENT_DISP_2L_OVL1_SOF 11 70 #define CMDQ_EVENT_DISP_WDMA0_SOF 12 71 #define CMDQ_EVENT_DISP_COLOR0_SOF 13 72 #define CMDQ_EVENT_DISP_CCORR0_SOF 14 73 #define CMDQ_EVENT_DISP_AAL0_SOF 15 74 #define CMDQ_EVENT_DISP_GAMMA0_SOF 16 75 #define CMDQ_EVENT_DISP_DITHER0_SOF 17 76 #define CMDQ_EVENT_DISP_PWM0_SOF 18 77 #define CMDQ_EVENT_DISP_DSI0_SOF 19 78 #define CMDQ_EVENT_DISP_DPI0_SOF 20 79 #define CMDQ_EVENT_DISP_POSTMASK0_SOF 21 80 #define CMDQ_EVENT_DISP_RSZ0_SOF 22 81 #define CMDQ_EVENT_MDP_AAL_SOF 23 82 #define CMDQ_EVENT_MDP_CCORR_SOF 24 83 #define CMDQ_EVENT_DISP_DBI0_SOF 25 84 #define CMDQ_EVENT_ISP_RELAY_SOF 26 85 #define CMDQ_EVENT_IPU_RELAY_SOF 27 86 #define CMDQ_EVENT_DISP_RDMA0_EOF 28 87 #define CMDQ_EVENT_DISP_RDMA1_EOF 29 88 #define CMDQ_EVENT_MDP_RDMA0_EOF 30 89 #define CMDQ_EVENT_MDP_RDMA1_EOF 31 90 #define CMDQ_EVENT_MDP_RSZ0_EOF 32 91 #define CMDQ_EVENT_MDP_RSZ1_EOF 33 92 #define CMDQ_EVENT_MDP_TDSHP_EOF 34 93 #define CMDQ_EVENT_MDP_WROT0_W_EOF 35 94 #define CMDQ_EVENT_MDP_WROT1_W_EOF 36 95 #define CMDQ_EVENT_DISP_OVL0_EOF 37 96 #define CMDQ_EVENT_DISP_2L_OVL0_EOF 38 97 #define CMDQ_EVENT_DISP_2L_OVL1_EOF 39 98 #define CMDQ_EVENT_DISP_WDMA0_EOF 40 99 #define CMDQ_EVENT_DISP_COLOR0_EOF 41 100 #define CMDQ_EVENT_DISP_CCORR0_EOF 42 101 #define CMDQ_EVENT_DISP_AAL0_EOF 43 102 #define CMDQ_EVENT_DISP_GAMMA0_EOF 44 103 #define CMDQ_EVENT_DISP_DITHER0_EOF 45 104 #define CMDQ_EVENT_DISP_DSI0_EOF 46 105 #define CMDQ_EVENT_DISP_DPI0_EOF 47 106 #define CMDQ_EVENT_DISP_RSZ0_EOF 49 107 #define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50 108 #define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51 109 #define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52 110 #define CMDQ_EVENT_MUTEX0_STREAM_EOF 130 111 #define CMDQ_EVENT_MUTEX1_STREAM_EOF 131 112 #define CMDQ_EVENT_MUTEX2_STREAM_EOF 132 113 #define CMDQ_EVENT_MUTEX3_STREAM_EOF 133 114 #define CMDQ_EVENT_MUTEX4_STREAM_EOF 134 115 #define CMDQ_EVENT_MUTEX5_STREAM_EOF 135 116 #define CMDQ_EVENT_MUTEX6_STREAM_EOF 136 117 #define CMDQ_EVENT_MUTEX7_STREAM_EOF 137 118 #define CMDQ_EVENT_MUTEX8_STREAM_EOF 138 119 #define CMDQ_EVENT_MUTEX9_STREAM_EOF 139 120 #define CMDQ_EVENT_MUTEX10_STREAM_EOF 140 121 #define CMDQ_EVENT_MUTEX11_STREAM_EOF 141 122 #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142 123 #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143 124 #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144 125 #define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145 126 #define CMDQ_EVENT_DSI0_TE 146 127 #define CMDQ_EVENT_DSI0_IRQ_EVENT 147 128 #define CMDQ_EVENT_DSI0_DONE_EVENT 148 129 #define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150 130 #define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151 131 #define CMDQ_EVENT_MDP_WROT0_RST_DONE 153 132 #define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154 133 #define CMDQ_EVENT_DISP_OVL0_RST_DONE 155 134 #define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156 135 #define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157 136 #define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257 137 #define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258 138 #define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259 139 #define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260 140 #define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261 141 #define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262 142 #define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263 143 #define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264 144 #define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265 145 #define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266 146 #define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267 147 #define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268 148 #define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269 149 #define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270 150 #define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271 151 #define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272 152 #define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273 153 #define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274 154 #define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275 155 #define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276 156 #define CMDQ_EVENT_AMD_FRAME_DONE 277 157 #define CMDQ_EVENT_MFB_DONE 278 158 #define CMDQ_EVENT_WPE_A_EOF 279 159 #define CMDQ_EVENT_VENC_EOF 289 160 #define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290 161 #define CMDQ_EVENT_JPEG_ENC_EOF 291 162 #define CMDQ_EVENT_VENC_MB_DONE 292 163 #define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293 164 #define CMDQ_EVENT_ISP_FRAME_DONE_A 321 165 #define CMDQ_EVENT_ISP_FRAME_DONE_B 322 166 #define CMDQ_EVENT_ISP_FRAME_DONE_C 323 167 #define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324 168 #define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325 169 #define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326 170 #define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327 171 #define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328 172 #define CMDQ_EVENT_ISP_TSF_DONE 329 173 #define CMDQ_EVENT_SENINF_0_FIFO_FULL 330 174 #define CMDQ_EVENT_SENINF_1_FIFO_FULL 331 175 #define CMDQ_EVENT_SENINF_2_FIFO_FULL 332 176 #define CMDQ_EVENT_SENINF_3_FIFO_FULL 333 177 #define CMDQ_EVENT_SENINF_4_FIFO_FULL 334 178 #define CMDQ_EVENT_SENINF_5_FIFO_FULL 335 179 #define CMDQ_EVENT_SENINF_6_FIFO_FULL 336 180 #define CMDQ_EVENT_SENINF_7_FIFO_FULL 337 181 #define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338 182 #define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339 183 #define CMDQ_EVENT_TG_OVRUN_C_INT 340 184 #define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341 185 #define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342 186 #define CMDQ_EVENT_TG_GRABERR_C_INT 343 187 #define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344 188 #define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345 189 #define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346 190 #define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347 191 #define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348 192 #define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349 193 #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353 194 #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354 195 #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355 196 #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356 197 #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385 198 #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386 199 #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387 200 #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388 201 #define CMDQ_EVENT_VDEC_EVENT_0 416 202 #define CMDQ_EVENT_VDEC_EVENT_1 417 203 #define CMDQ_EVENT_VDEC_EVENT_2 418 204 #define CMDQ_EVENT_VDEC_EVENT_3 419 205 #define CMDQ_EVENT_VDEC_EVENT_4 420 206 #define CMDQ_EVENT_VDEC_EVENT_5 421 207 #define CMDQ_EVENT_VDEC_EVENT_6 422 208 #define CMDQ_EVENT_VDEC_EVENT_7 423 209 #define CMDQ_EVENT_VDEC_EVENT_8 424 210 #define CMDQ_EVENT_VDEC_EVENT_9 425 211 #define CMDQ_EVENT_VDEC_EVENT_10 426 212 #define CMDQ_EVENT_VDEC_EVENT_11 427 213 #define CMDQ_EVENT_VDEC_EVENT_12 428 214 #define CMDQ_EVENT_VDEC_EVENT_13 429 215 #define CMDQ_EVENT_VDEC_EVENT_14 430 216 #define CMDQ_EVENT_VDEC_EVENT_15 431 217 #define CMDQ_EVENT_FDVT_DONE 449 218 #define CMDQ_EVENT_FE_DONE 450 219 #define CMDQ_EVENT_RSC_EOF 451 220 #define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452 221 #define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453 222 #define CMDQ_EVENT_DSI0_TE_INFRA 898 223 224 #endif 225
Indexes created Tue Sep 30 10:09:55 GMT 2025