1/* $NetBSD: mt8186-gce.h,v 1.1.1.1 2026/01/18 05:21:43 skrll Exp $ */ 2 3/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 4/* 5 * Copyright (C) 2022 MediaTek Inc. 6 * Author: Yongqiang Niu <yongqiang.niu@mediatek.com> 7 */ 8 9#ifndef _DT_BINDINGS_GCE_MT8186_H 10#define _DT_BINDINGS_GCE_MT8186_H 11 12/* assign timeout 0 also means default */ 13#define CMDQ_NO_TIMEOUT 0xffffffff 14#define CMDQ_TIMEOUT_DEFAULT 1000 15 16/* GCE thread priority */ 17#define CMDQ_THR_PRIO_LOWEST 0 18#define CMDQ_THR_PRIO_1 1 19#define CMDQ_THR_PRIO_2 2 20#define CMDQ_THR_PRIO_3 3 21#define CMDQ_THR_PRIO_4 4 22#define CMDQ_THR_PRIO_5 5 23#define CMDQ_THR_PRIO_6 6 24#define CMDQ_THR_PRIO_HIGHEST 7 25 26/* CPR count in 32bit register */ 27#define GCE_CPR_COUNT 1312 28 29/* GCE subsys table */ 30#define SUBSYS_1300XXXX 0 31#define SUBSYS_1400XXXX 1 32#define SUBSYS_1401XXXX 2 33#define SUBSYS_1402XXXX 3 34#define SUBSYS_1502XXXX 4 35#define SUBSYS_1582XXXX 5 36#define SUBSYS_1B00XXXX 6 37#define SUBSYS_1C00XXXX 7 38#define SUBSYS_1C10XXXX 8 39#define SUBSYS_1000XXXX 9 40#define SUBSYS_1001XXXX 10 41#define SUBSYS_1020XXXX 11 42#define SUBSYS_1021XXXX 12 43#define SUBSYS_1022XXXX 13 44#define SUBSYS_1023XXXX 14 45#define SUBSYS_1060XXXX 15 46#define SUBSYS_1602XXXX 16 47#define SUBSYS_1608XXXX 17 48#define SUBSYS_1700XXXX 18 49#define SUBSYS_1701XXXX 19 50#define SUBSYS_1702XXXX 20 51#define SUBSYS_1703XXXX 21 52#define SUBSYS_1706XXXX 22 53#define SUBSYS_1A00XXXX 23 54#define SUBSYS_1A01XXXX 24 55#define SUBSYS_1A02XXXX 25 56#define SUBSYS_1A03XXXX 26 57#define SUBSYS_1A04XXXX 27 58#define SUBSYS_1A05XXXX 28 59#define SUBSYS_1A06XXXX 29 60#define SUBSYS_NO_SUPPORT 99 61 62/* GCE General Purpose Register (GPR) support 63 * Leave note for scenario usage here 64 */ 65/* GCE: write mask */ 66#define GCE_GPR_R00 0x00 67#define GCE_GPR_R01 0x01 68/* MDP: P1: JPEG dest */ 69#define GCE_GPR_R02 0x02 70#define GCE_GPR_R03 0x03 71/* MDP: PQ color */ 72#define GCE_GPR_R04 0x04 73/* MDP: 2D sharpness */ 74#define GCE_GPR_R05 0x05 75/* DISP: poll esd */ 76#define GCE_GPR_R06 0x06 77#define GCE_GPR_R07 0x07 78/* MDP: P4: 2D sharpness dst */ 79#define GCE_GPR_R08 0x08 80#define GCE_GPR_R09 0x09 81/* VCU: poll with timeout for GPR timer */ 82#define GCE_GPR_R10 0x0A 83#define GCE_GPR_R11 0x0B 84/* CMDQ: debug */ 85#define GCE_GPR_R12 0x0C 86#define GCE_GPR_R13 0x0D 87/* CMDQ: P7: debug */ 88#define GCE_GPR_R14 0x0E 89#define GCE_GPR_R15 0x0F 90 91/* GCE hardware events */ 92/* VDEC */ 93#define CMDQ_EVENT_LINE_COUNT_THRESHOLD_INTERRUPT 0 94#define CMDQ_EVENT_VDEC_INT 1 95#define CMDQ_EVENT_VDEC_PAUSE 2 96#define CMDQ_EVENT_VDEC_DEC_ERROR 3 97#define CMDQ_EVENT_MDEC_TIMEOUT 4 98#define CMDQ_EVENT_DRAM_ACCESS_DONE 5 99#define CMDQ_EVENT_INI_FETCH_RDY 6 100#define CMDQ_EVENT_PROCESS_FLAG 7 101#define CMDQ_EVENT_SEARCH_START_CODE_DONE 8 102#define CMDQ_EVENT_REF_REORDER_DONE 9 103#define CMDQ_EVENT_WP_TBLE_DONE 10 104#define CMDQ_EVENT_COUNT_SRAM_CLR_DONE 11 105#define CMDQ_EVENT_GCE_CNT_OP_THRESHOLD 15 106#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_0 16 107#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_1 17 108#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_2 18 109#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_3 19 110#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_4 20 111#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_5 21 112#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_6 22 113#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_7 23 114#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_8 24 115#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_9 25 116#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_10 26 117#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_11 27 118#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_12 28 119#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_13 29 120#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_14 30 121#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_15 31 122#define CMDQ_EVENT_WPE_GCE_FRAME_DONE 32 123 124/* CAM */ 125#define CMDQ_EVENT_ISP_FRAME_DONE_A 65 126#define CMDQ_EVENT_ISP_FRAME_DONE_B 66 127#define CMDQ_EVENT_CAMSV1_PASS1_DONE 70 128#define CMDQ_EVENT_CAMSV2_PASS1_DONE 71 129#define CMDQ_EVENT_CAMSV3_PASS1_DONE 72 130#define CMDQ_EVENT_MRAW_0_PASS1_DONE 73 131#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75 132#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76 133#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77 134#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78 135#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79 136#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80 137#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81 138#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82 139#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83 140#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84 141#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85 142#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86 143#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87 144#define CMDQ_EVENT_TG_OVRUN_A_INT 88 145#define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89 146#define CMDQ_EVENT_TG_OVRUN_B_INT 90 147#define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91 148#define CMDQ_EVENT_TG_OVRUN_M0_INT 94 149#define CMDQ_EVENT_R1_ERROR_M0_INT 95 150#define CMDQ_EVENT_TG_GRABERR_M0_INT 96 151#define CMDQ_EVENT_TG_GRABERR_A_INT 98 152#define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99 153#define CMDQ_EVENT_TG_GRABERR_B_INT 100 154#define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101 155/* VENC */ 156#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129 157#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130 158#define CMDQ_EVENT_JPGENC_CMDQ_DONE 131 159#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132 160#define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133 161#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136 162#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137 163#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138 164/* IPE */ 165#define CMDQ_EVENT_FDVT_DONE 161 166#define CMDQ_EVENT_FE_DONE 162 167#define CMDQ_EVENT_RSC_DONE 163 168#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 164 169#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 165 170/* IMG2 */ 171#define CMDQ_EVENT_GCE_IMG2_EVENT0 193 172#define CMDQ_EVENT_GCE_IMG2_EVENT1 194 173#define CMDQ_EVENT_GCE_IMG2_EVENT2 195 174#define CMDQ_EVENT_GCE_IMG2_EVENT3 196 175#define CMDQ_EVENT_GCE_IMG2_EVENT4 197 176#define CMDQ_EVENT_GCE_IMG2_EVENT5 198 177#define CMDQ_EVENT_GCE_IMG2_EVENT6 199 178#define CMDQ_EVENT_GCE_IMG2_EVENT7 200 179#define CMDQ_EVENT_GCE_IMG2_EVENT8 201 180#define CMDQ_EVENT_GCE_IMG2_EVENT9 202 181#define CMDQ_EVENT_GCE_IMG2_EVENT10 203 182#define CMDQ_EVENT_GCE_IMG2_EVENT11 204 183#define CMDQ_EVENT_GCE_IMG2_EVENT12 205 184#define CMDQ_EVENT_GCE_IMG2_EVENT13 206 185#define CMDQ_EVENT_GCE_IMG2_EVENT14 207 186#define CMDQ_EVENT_GCE_IMG2_EVENT15 208 187#define CMDQ_EVENT_GCE_IMG2_EVENT16 209 188#define CMDQ_EVENT_GCE_IMG2_EVENT17 210 189#define CMDQ_EVENT_GCE_IMG2_EVENT18 211 190#define CMDQ_EVENT_GCE_IMG2_EVENT19 212 191#define CMDQ_EVENT_GCE_IMG2_EVENT20 213 192#define CMDQ_EVENT_GCE_IMG2_EVENT21 214 193#define CMDQ_EVENT_GCE_IMG2_EVENT22 215 194#define CMDQ_EVENT_GCE_IMG2_EVENT23 216 195/* IMG1 */ 196#define CMDQ_EVENT_GCE_IMG1_EVENT0 225 197#define CMDQ_EVENT_GCE_IMG1_EVENT1 226 198#define CMDQ_EVENT_GCE_IMG1_EVENT2 227 199#define CMDQ_EVENT_GCE_IMG1_EVENT3 228 200#define CMDQ_EVENT_GCE_IMG1_EVENT4 229 201#define CMDQ_EVENT_GCE_IMG1_EVENT5 230 202#define CMDQ_EVENT_GCE_IMG1_EVENT6 231 203#define CMDQ_EVENT_GCE_IMG1_EVENT7 232 204#define CMDQ_EVENT_GCE_IMG1_EVENT8 233 205#define CMDQ_EVENT_GCE_IMG1_EVENT9 234 206#define CMDQ_EVENT_GCE_IMG1_EVENT10 235 207#define CMDQ_EVENT_GCE_IMG1_EVENT11 236 208#define CMDQ_EVENT_GCE_IMG1_EVENT12 237 209#define CMDQ_EVENT_GCE_IMG1_EVENT13 238 210#define CMDQ_EVENT_GCE_IMG1_EVENT14 239 211#define CMDQ_EVENT_GCE_IMG1_EVENT15 240 212#define CMDQ_EVENT_GCE_IMG1_EVENT16 241 213#define CMDQ_EVENT_GCE_IMG1_EVENT17 242 214#define CMDQ_EVENT_GCE_IMG1_EVENT18 243 215#define CMDQ_EVENT_GCE_IMG1_EVENT19 244 216#define CMDQ_EVENT_GCE_IMG1_EVENT20 245 217#define CMDQ_EVENT_GCE_IMG1_EVENT21 246 218#define CMDQ_EVENT_GCE_IMG1_EVENT22 247 219#define CMDQ_EVENT_GCE_IMG1_EVENT23 248 220/* MDP */ 221#define CMDQ_EVENT_MDP_RDMA0_SOF 256 222#define CMDQ_EVENT_MDP_RDMA1_SOF 257 223#define CMDQ_EVENT_MDP_AAL0_SOF 258 224#define CMDQ_EVENT_MDP_AAL1_SOF 259 225#define CMDQ_EVENT_MDP_HDR0_SOF 260 226#define CMDQ_EVENT_MDP_RSZ0_SOF 261 227#define CMDQ_EVENT_MDP_RSZ1_SOF 262 228#define CMDQ_EVENT_MDP_WROT0_SOF 263 229#define CMDQ_EVENT_MDP_WROT1_SOF 264 230#define CMDQ_EVENT_MDP_TDSHP0_SOF 265 231#define CMDQ_EVENT_MDP_TDSHP1_SOF 266 232#define CMDQ_EVENT_IMG_DL_RELAY0_SOF 267 233#define CMDQ_EVENT_IMG_DL_RELAY1_SOF 268 234#define CMDQ_EVENT_MDP_COLOR0_SOF 269 235#define CMDQ_EVENT_MDP_WROT3_FRAME_DONE 288 236#define CMDQ_EVENT_MDP_WROT2_FRAME_DONE 289 237#define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290 238#define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291 239#define CMDQ_EVENT_MDP_TDSHP3_FRAME_DONE 292 240#define CMDQ_EVENT_MDP_TDSHP2_FRAME_DONE 293 241#define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294 242#define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295 243#define CMDQ_EVENT_MDP_RSZ3_FRAME_DONE 296 244#define CMDQ_EVENT_MDP_RSZ2_FRAME_DONE 297 245#define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 298 246#define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 299 247#define CMDQ_EVENT_MDP_RDMA3_FRAME_DONE 300 248#define CMDQ_EVENT_MDP_RDMA2_FRAME_DONE 301 249#define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 302 250#define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 303 251#define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 304 252#define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 305 253#define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 306 254#define CMDQ_EVENT_MDP_AAL3_FRAME_DONE 307 255#define CMDQ_EVENT_MDP_AAL2_FRAME_DONE 308 256#define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 309 257#define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 310 258#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320 259#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321 260#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322 261#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323 262#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324 263#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325 264#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326 265#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327 266#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328 267#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329 268#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330 269#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331 270#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332 271#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333 272#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334 273#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335 274#define CMDQ_EVENT_MDP_WROT3_SW_RST_DONE_ENG_EVENT 336 275#define CMDQ_EVENT_MDP_WROT2_SW_RST_DONE_ENG_EVENT 337 276#define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338 277#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339 278#define CMDQ_EVENT_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 340 279#define CMDQ_EVENT_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 341 280#define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342 281#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343 282/* DISP */ 283#define CMDQ_EVENT_DISP_OVL0_SOF 384 284#define CMDQ_EVENT_DISP_OVL0_2L_SOF 385 285#define CMDQ_EVENT_DISP_RDMA0_SOF 386 286#define CMDQ_EVENT_DISP_RSZ0_SOF 387 287#define CMDQ_EVENT_DISP_COLOR0_SOF 388 288#define CMDQ_EVENT_DISP_CCORR0_SOF 389 289#define CMDQ_EVENT_DISP_CCORR1_SOF 390 290#define CMDQ_EVENT_DISP_AAL0_SOF 391 291#define CMDQ_EVENT_DISP_GAMMA0_SOF 392 292#define CMDQ_EVENT_DISP_POSTMASK0_SOF 393 293#define CMDQ_EVENT_DISP_DITHER0_SOF 394 294#define CMDQ_EVENT_DISP_CM0_SOF 395 295#define CMDQ_EVENT_DISP_SPR0_SOF 396 296#define CMDQ_EVENT_DISP_DSC_WRAP0_SOF 397 297#define CMDQ_EVENT_DSI0_SOF 398 298#define CMDQ_EVENT_DISP_WDMA0_SOF 399 299#define CMDQ_EVENT_DISP_PWM0_SOF 400 300#define CMDQ_EVENT_DSI0_FRAME_DONE 410 301#define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 411 302#define CMDQ_EVENT_DISP_SPR0_FRAME_DONE 412 303#define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 413 304#define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 414 305#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 415 306#define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 416 307#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 417 308#define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 418 309#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 420 310#define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 421 311#define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 422 312#define CMDQ_EVENT_DISP_CM0_FRAME_DONE 423 313#define CMDQ_EVENT_DISP_CCORR1_FRAME_DONE 424 314#define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 425 315#define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 426 316#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434 317#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435 318#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436 319#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437 320#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438 321#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439 322#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440 323#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441 324#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442 325#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443 326#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444 327#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445 328#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446 329#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447 330#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448 331#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449 332#define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450 333#define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451 334#define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452 335#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453 336#define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454 337#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455 338#define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 456 339#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 457 340#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 458 341#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 459 342#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 460 343#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 461 344#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 462 345#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 463 346#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 464 347#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 465 348#define CMDQ_EVENT_OUT_EVENT_0 898 349 350/* CMDQ sw tokens 351 * Following definitions are gce sw token which may use by clients 352 * event operation API. 353 * Note that token 512 to 639 may set secure 354 */ 355 356/* end of hw event and begin of sw token */ 357#define CMDQ_MAX_HW_EVENT 512 358 359/* Config thread notify trigger thread */ 360#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640 361/* Trigger thread notify config thread */ 362#define CMDQ_SYNC_TOKEN_STREAM_EOF 641 363/* Block Trigger thread until the ESD check finishes. */ 364#define CMDQ_SYNC_TOKEN_ESD_EOF 642 365#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643 366/* check CABC setup finish */ 367#define CMDQ_SYNC_TOKEN_CABC_EOF 644 368 369/* Notify normal CMDQ there are some secure task done 370 * MUST NOT CHANGE, this token sync with secure world 371 */ 372#define CMDQ_SYNC_SECURE_THR_EOF 647 373 374/* CMDQ use sw token */ 375#define CMDQ_SYNC_TOKEN_USER_0 649 376#define CMDQ_SYNC_TOKEN_USER_1 650 377#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651 378#define CMDQ_SYNC_TOKEN_TPR_LOCK 652 379 380/* ISP sw token */ 381#define CMDQ_SYNC_TOKEN_MSS 665 382#define CMDQ_SYNC_TOKEN_MSF 666 383 384/* DISP sw token */ 385#define CMDQ_SYNC_TOKEN_SODI 671 386 387/* GPR access tokens (for register backup) 388 * There are 15 32-bit GPR, 3 GPR form a set 389 * (64-bit for address, 32-bit for value) 390 * MUST NOT CHANGE, these tokens sync with MDP 391 */ 392#define CMDQ_SYNC_TOKEN_GPR_SET_0 700 393#define CMDQ_SYNC_TOKEN_GPR_SET_1 701 394#define CMDQ_SYNC_TOKEN_GPR_SET_2 702 395#define CMDQ_SYNC_TOKEN_GPR_SET_3 703 396#define CMDQ_SYNC_TOKEN_GPR_SET_4 704 397 398/* Resource lock event to control resource in GCE thread */ 399#define CMDQ_SYNC_RESOURCE_WROT0 710 400#define CMDQ_SYNC_RESOURCE_WROT1 711 401 402/* event for gpr timer, used in sleep and poll with timeout */ 403#define CMDQ_TOKEN_GPR_TIMER_R0 994 404#define CMDQ_TOKEN_GPR_TIMER_R1 995 405#define CMDQ_TOKEN_GPR_TIMER_R2 996 406#define CMDQ_TOKEN_GPR_TIMER_R3 997 407#define CMDQ_TOKEN_GPR_TIMER_R4 998 408#define CMDQ_TOKEN_GPR_TIMER_R5 999 409#define CMDQ_TOKEN_GPR_TIMER_R6 1000 410#define CMDQ_TOKEN_GPR_TIMER_R7 1001 411#define CMDQ_TOKEN_GPR_TIMER_R8 1002 412#define CMDQ_TOKEN_GPR_TIMER_R9 1003 413#define CMDQ_TOKEN_GPR_TIMER_R10 1004 414#define CMDQ_TOKEN_GPR_TIMER_R11 1005 415#define CMDQ_TOKEN_GPR_TIMER_R12 1006 416#define CMDQ_TOKEN_GPR_TIMER_R13 1007 417#define CMDQ_TOKEN_GPR_TIMER_R14 1008 418#define CMDQ_TOKEN_GPR_TIMER_R15 1009 419 420#define CMDQ_EVENT_MAX 0x3FF 421/* CMDQ sw tokens END */ 422 423#endif 424