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      1 /*	$NetBSD: qcom,msm8996.h,v 1.1.1.1 2026/01/18 05:21:45 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
      4 /*
      5  * Qualcomm MSM8996 interconnect IDs
      6  *
      7  * Copyright (c) 2021 Yassine Oudjana <y.oudjana (at) protonmail.com>
      8  */
      9 
     10 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
     11 #define __DT_BINDINGS_INTERCONNECT_QCOM_MSM8996_H
     12 
     13 /* A0NOC */
     14 #define MASTER_PCIE_0			0
     15 #define MASTER_PCIE_1			1
     16 #define MASTER_PCIE_2			2
     17 
     18 /* A1NOC */
     19 #define MASTER_CNOC_A1NOC		0
     20 #define MASTER_CRYPTO_CORE0		1
     21 #define MASTER_PNOC_A1NOC		2
     22 
     23 /* A2NOC */
     24 #define MASTER_USB3			0
     25 #define MASTER_IPA			1
     26 #define MASTER_UFS			2
     27 
     28 /* BIMC */
     29 #define MASTER_AMPSS_M0			0
     30 #define MASTER_GRAPHICS_3D		1
     31 #define MASTER_MNOC_BIMC		2
     32 #define MASTER_SNOC_BIMC		3
     33 #define SLAVE_EBI_CH0			4
     34 #define SLAVE_HMSS_L3			5
     35 #define SLAVE_BIMC_SNOC_0		6
     36 #define SLAVE_BIMC_SNOC_1		7
     37 
     38 /* CNOC */
     39 #define MASTER_SNOC_CNOC		0
     40 #define MASTER_QDSS_DAP			1
     41 #define SLAVE_CNOC_A1NOC		2
     42 #define SLAVE_CLK_CTL			3
     43 #define SLAVE_TCSR			4
     44 #define SLAVE_TLMM			5
     45 #define SLAVE_CRYPTO_0_CFG		6
     46 #define SLAVE_MPM			7
     47 #define SLAVE_PIMEM_CFG			8
     48 #define SLAVE_IMEM_CFG			9
     49 #define SLAVE_MESSAGE_RAM		10
     50 #define SLAVE_BIMC_CFG			11
     51 #define SLAVE_PMIC_ARB			12
     52 #define SLAVE_PRNG			13
     53 #define SLAVE_DCC_CFG			14
     54 #define SLAVE_RBCPR_MX			15
     55 #define SLAVE_QDSS_CFG			16
     56 #define SLAVE_RBCPR_CX			17
     57 #define SLAVE_QDSS_RBCPR_APU		18
     58 #define SLAVE_CNOC_MNOC_CFG		19
     59 #define SLAVE_SNOC_CFG			20
     60 #define SLAVE_SNOC_MPU_CFG		21
     61 #define SLAVE_EBI1_PHY_CFG		22
     62 #define SLAVE_A0NOC_CFG			23
     63 #define SLAVE_PCIE_1_CFG		24
     64 #define SLAVE_PCIE_2_CFG		25
     65 #define SLAVE_PCIE_0_CFG		26
     66 #define SLAVE_PCIE20_AHB2PHY		27
     67 #define SLAVE_A0NOC_MPU_CFG		28
     68 #define SLAVE_UFS_CFG			29
     69 #define SLAVE_A1NOC_CFG			30
     70 #define SLAVE_A1NOC_MPU_CFG		31
     71 #define SLAVE_A2NOC_CFG			32
     72 #define SLAVE_A2NOC_MPU_CFG		33
     73 #define SLAVE_SSC_CFG			34
     74 #define SLAVE_A0NOC_SMMU_CFG		35
     75 #define SLAVE_A1NOC_SMMU_CFG		36
     76 #define SLAVE_A2NOC_SMMU_CFG		37
     77 #define SLAVE_LPASS_SMMU_CFG		38
     78 #define SLAVE_CNOC_MNOC_MMSS_CFG	39
     79 
     80 /* MNOC */
     81 #define MASTER_CNOC_MNOC_CFG		0
     82 #define MASTER_CPP			1
     83 #define MASTER_JPEG			2
     84 #define MASTER_MDP_PORT0		3
     85 #define MASTER_MDP_PORT1		4
     86 #define MASTER_ROTATOR			5
     87 #define MASTER_VIDEO_P0			6
     88 #define MASTER_VFE			7
     89 #define MASTER_SNOC_VMEM		8
     90 #define MASTER_VIDEO_P0_OCMEM		9
     91 #define MASTER_CNOC_MNOC_MMSS_CFG	10
     92 #define SLAVE_MNOC_BIMC			11
     93 #define SLAVE_VMEM			12
     94 #define SLAVE_SERVICE_MNOC		13
     95 #define SLAVE_MMAGIC_CFG		14
     96 #define SLAVE_CPR_CFG			15
     97 #define SLAVE_MISC_CFG			16
     98 #define SLAVE_VENUS_THROTTLE_CFG	17
     99 #define SLAVE_VENUS_CFG			18
    100 #define SLAVE_VMEM_CFG			19
    101 #define SLAVE_DSA_CFG			20
    102 #define SLAVE_MMSS_CLK_CFG		21
    103 #define SLAVE_DSA_MPU_CFG		22
    104 #define SLAVE_MNOC_MPU_CFG		23
    105 #define SLAVE_DISPLAY_CFG		24
    106 #define SLAVE_DISPLAY_THROTTLE_CFG	25
    107 #define SLAVE_CAMERA_CFG		26
    108 #define SLAVE_CAMERA_THROTTLE_CFG	27
    109 #define SLAVE_GRAPHICS_3D_CFG		28
    110 #define SLAVE_SMMU_MDP_CFG		29
    111 #define SLAVE_SMMU_ROT_CFG		30
    112 #define SLAVE_SMMU_VENUS_CFG		31
    113 #define SLAVE_SMMU_CPP_CFG		32
    114 #define SLAVE_SMMU_JPEG_CFG		33
    115 #define SLAVE_SMMU_VFE_CFG		34
    116 
    117 /* PNOC */
    118 #define MASTER_SNOC_PNOC		0
    119 #define MASTER_SDCC_1			1
    120 #define MASTER_SDCC_2			2
    121 #define MASTER_SDCC_4			3
    122 #define MASTER_USB_HS			4
    123 #define MASTER_BLSP_1			5
    124 #define MASTER_BLSP_2			6
    125 #define MASTER_TSIF			7
    126 #define SLAVE_PNOC_A1NOC		8
    127 #define SLAVE_USB_HS			9
    128 #define SLAVE_SDCC_2			10
    129 #define SLAVE_SDCC_4			11
    130 #define SLAVE_TSIF			12
    131 #define SLAVE_BLSP_2			13
    132 #define SLAVE_SDCC_1			14
    133 #define SLAVE_BLSP_1			15
    134 #define SLAVE_PDM			16
    135 #define SLAVE_AHB2PHY			17
    136 
    137 /* SNOC */
    138 #define MASTER_HMSS			0
    139 #define MASTER_QDSS_BAM			1
    140 #define MASTER_SNOC_CFG			2
    141 #define MASTER_BIMC_SNOC_0		3
    142 #define MASTER_BIMC_SNOC_1		4
    143 #define MASTER_A0NOC_SNOC		5
    144 #define MASTER_A1NOC_SNOC		6
    145 #define MASTER_A2NOC_SNOC		7
    146 #define MASTER_QDSS_ETR			8
    147 #define SLAVE_A0NOC_SNOC		9
    148 #define SLAVE_A1NOC_SNOC		10
    149 #define SLAVE_A2NOC_SNOC		11
    150 #define SLAVE_HMSS			12
    151 #define SLAVE_LPASS			13
    152 #define SLAVE_USB3			14
    153 #define SLAVE_SNOC_BIMC			15
    154 #define SLAVE_SNOC_CNOC			16
    155 #define SLAVE_IMEM			17
    156 #define SLAVE_PIMEM			18
    157 #define SLAVE_SNOC_VMEM			19
    158 #define SLAVE_SNOC_PNOC			20
    159 #define SLAVE_QDSS_STM			21
    160 #define SLAVE_PCIE_0			22
    161 #define SLAVE_PCIE_1			23
    162 #define SLAVE_PCIE_2			24
    163 #define SLAVE_SERVICE_SNOC		25
    164 
    165 #endif
    166