1 1.1 skrll /* $NetBSD: qcom,qcs404.h,v 1.1.1.1 2020/01/03 14:33:03 skrll Exp $ */ 2 1.1 skrll 3 1.1 skrll /* SPDX-License-Identifier: GPL-2.0 */ 4 1.1 skrll /* 5 1.1 skrll * Qualcomm interconnect IDs 6 1.1 skrll * 7 1.1 skrll * Copyright (c) 2019, Linaro Ltd. 8 1.1 skrll * Author: Georgi Djakov <georgi.djakov (at) linaro.org> 9 1.1 skrll */ 10 1.1 skrll 11 1.1 skrll #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H 12 1.1 skrll #define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H 13 1.1 skrll 14 1.1 skrll #define MASTER_AMPSS_M0 0 15 1.1 skrll #define MASTER_OXILI 1 16 1.1 skrll #define MASTER_MDP_PORT0 2 17 1.1 skrll #define MASTER_SNOC_BIMC_1 3 18 1.1 skrll #define MASTER_TCU_0 4 19 1.1 skrll #define SLAVE_EBI_CH0 5 20 1.1 skrll #define SLAVE_BIMC_SNOC 6 21 1.1 skrll 22 1.1 skrll #define MASTER_SPDM 0 23 1.1 skrll #define MASTER_BLSP_1 1 24 1.1 skrll #define MASTER_BLSP_2 2 25 1.1 skrll #define MASTER_XI_USB_HS1 3 26 1.1 skrll #define MASTER_CRYPT0 4 27 1.1 skrll #define MASTER_SDCC_1 5 28 1.1 skrll #define MASTER_SDCC_2 6 29 1.1 skrll #define MASTER_SNOC_PCNOC 7 30 1.1 skrll #define MASTER_QPIC 8 31 1.1 skrll #define PCNOC_INT_0 9 32 1.1 skrll #define PCNOC_INT_2 10 33 1.1 skrll #define PCNOC_INT_3 11 34 1.1 skrll #define PCNOC_S_0 12 35 1.1 skrll #define PCNOC_S_1 13 36 1.1 skrll #define PCNOC_S_2 14 37 1.1 skrll #define PCNOC_S_3 15 38 1.1 skrll #define PCNOC_S_4 16 39 1.1 skrll #define PCNOC_S_6 17 40 1.1 skrll #define PCNOC_S_7 18 41 1.1 skrll #define PCNOC_S_8 19 42 1.1 skrll #define PCNOC_S_9 20 43 1.1 skrll #define PCNOC_S_10 21 44 1.1 skrll #define PCNOC_S_11 22 45 1.1 skrll #define SLAVE_SPDM 23 46 1.1 skrll #define SLAVE_PDM 24 47 1.1 skrll #define SLAVE_PRNG 25 48 1.1 skrll #define SLAVE_TCSR 26 49 1.1 skrll #define SLAVE_SNOC_CFG 27 50 1.1 skrll #define SLAVE_MESSAGE_RAM 28 51 1.1 skrll #define SLAVE_DISP_SS_CFG 29 52 1.1 skrll #define SLAVE_GPU_CFG 30 53 1.1 skrll #define SLAVE_BLSP_1 31 54 1.1 skrll #define SLAVE_BLSP_2 32 55 1.1 skrll #define SLAVE_TLMM_NORTH 33 56 1.1 skrll #define SLAVE_PCIE 34 57 1.1 skrll #define SLAVE_ETHERNET 35 58 1.1 skrll #define SLAVE_TLMM_EAST 36 59 1.1 skrll #define SLAVE_TCU 37 60 1.1 skrll #define SLAVE_PMIC_ARB 38 61 1.1 skrll #define SLAVE_SDCC_1 39 62 1.1 skrll #define SLAVE_SDCC_2 40 63 1.1 skrll #define SLAVE_TLMM_SOUTH 41 64 1.1 skrll #define SLAVE_USB_HS 42 65 1.1 skrll #define SLAVE_USB3 43 66 1.1 skrll #define SLAVE_CRYPTO_0_CFG 44 67 1.1 skrll #define SLAVE_PCNOC_SNOC 45 68 1.1 skrll 69 1.1 skrll #define MASTER_QDSS_BAM 0 70 1.1 skrll #define MASTER_BIMC_SNOC 1 71 1.1 skrll #define MASTER_PCNOC_SNOC 2 72 1.1 skrll #define MASTER_QDSS_ETR 3 73 1.1 skrll #define MASTER_EMAC 4 74 1.1 skrll #define MASTER_PCIE 5 75 1.1 skrll #define MASTER_USB3 6 76 1.1 skrll #define QDSS_INT 7 77 1.1 skrll #define SNOC_INT_0 8 78 1.1 skrll #define SNOC_INT_1 9 79 1.1 skrll #define SNOC_INT_2 10 80 1.1 skrll #define SLAVE_KPSS_AHB 11 81 1.1 skrll #define SLAVE_WCSS 12 82 1.1 skrll #define SLAVE_SNOC_BIMC_1 13 83 1.1 skrll #define SLAVE_IMEM 14 84 1.1 skrll #define SLAVE_SNOC_PCNOC 15 85 1.1 skrll #define SLAVE_QDSS_STM 16 86 1.1 skrll #define SLAVE_CATS_0 17 87 1.1 skrll #define SLAVE_CATS_1 18 88 1.1 skrll #define SLAVE_LPASS 19 89 1.1 skrll 90 1.1 skrll #endif 91