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      1 /*	$NetBSD: qcom,qcs404.h,v 1.1.1.1 2020/01/03 14:33:03 skrll Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 /*
      5  * Qualcomm interconnect IDs
      6  *
      7  * Copyright (c) 2019, Linaro Ltd.
      8  * Author: Georgi Djakov <georgi.djakov (at) linaro.org>
      9  */
     10 
     11 #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
     12 #define __DT_BINDINGS_INTERCONNECT_QCOM_QCS404_H
     13 
     14 #define MASTER_AMPSS_M0			0
     15 #define MASTER_OXILI			1
     16 #define MASTER_MDP_PORT0		2
     17 #define MASTER_SNOC_BIMC_1		3
     18 #define MASTER_TCU_0			4
     19 #define SLAVE_EBI_CH0			5
     20 #define SLAVE_BIMC_SNOC			6
     21 
     22 #define MASTER_SPDM			0
     23 #define MASTER_BLSP_1			1
     24 #define MASTER_BLSP_2			2
     25 #define MASTER_XI_USB_HS1		3
     26 #define MASTER_CRYPT0			4
     27 #define MASTER_SDCC_1			5
     28 #define MASTER_SDCC_2			6
     29 #define MASTER_SNOC_PCNOC		7
     30 #define MASTER_QPIC			8
     31 #define PCNOC_INT_0			9
     32 #define PCNOC_INT_2			10
     33 #define PCNOC_INT_3			11
     34 #define PCNOC_S_0			12
     35 #define PCNOC_S_1			13
     36 #define PCNOC_S_2			14
     37 #define PCNOC_S_3			15
     38 #define PCNOC_S_4			16
     39 #define PCNOC_S_6			17
     40 #define PCNOC_S_7			18
     41 #define PCNOC_S_8			19
     42 #define PCNOC_S_9			20
     43 #define PCNOC_S_10			21
     44 #define PCNOC_S_11			22
     45 #define SLAVE_SPDM			23
     46 #define SLAVE_PDM			24
     47 #define SLAVE_PRNG			25
     48 #define SLAVE_TCSR			26
     49 #define SLAVE_SNOC_CFG			27
     50 #define SLAVE_MESSAGE_RAM		28
     51 #define SLAVE_DISP_SS_CFG		29
     52 #define SLAVE_GPU_CFG			30
     53 #define SLAVE_BLSP_1			31
     54 #define SLAVE_BLSP_2			32
     55 #define SLAVE_TLMM_NORTH		33
     56 #define SLAVE_PCIE			34
     57 #define SLAVE_ETHERNET			35
     58 #define SLAVE_TLMM_EAST			36
     59 #define SLAVE_TCU			37
     60 #define SLAVE_PMIC_ARB			38
     61 #define SLAVE_SDCC_1			39
     62 #define SLAVE_SDCC_2			40
     63 #define SLAVE_TLMM_SOUTH		41
     64 #define SLAVE_USB_HS			42
     65 #define SLAVE_USB3			43
     66 #define SLAVE_CRYPTO_0_CFG		44
     67 #define SLAVE_PCNOC_SNOC		45
     68 
     69 #define MASTER_QDSS_BAM			0
     70 #define MASTER_BIMC_SNOC		1
     71 #define MASTER_PCNOC_SNOC		2
     72 #define MASTER_QDSS_ETR			3
     73 #define MASTER_EMAC			4
     74 #define MASTER_PCIE			5
     75 #define MASTER_USB3			6
     76 #define QDSS_INT			7
     77 #define SNOC_INT_0			8
     78 #define SNOC_INT_1			9
     79 #define SNOC_INT_2			10
     80 #define SLAVE_KPSS_AHB			11
     81 #define SLAVE_WCSS			12
     82 #define SLAVE_SNOC_BIMC_1		13
     83 #define SLAVE_IMEM			14
     84 #define SLAVE_SNOC_PCNOC		15
     85 #define SLAVE_QDSS_STM			16
     86 #define SLAVE_CATS_0			17
     87 #define SLAVE_CATS_1			18
     88 #define SLAVE_LPASS			19
     89 
     90 #endif
     91