1/*	$NetBSD: mt8186-memory-port.h,v 1.1.1.1 2026/01/18 05:21:48 skrll Exp $	*/
2
3/* SPDX-License-Identifier: GPL-2.0-only */
4/*
5 * Copyright (c) 2022 MediaTek Inc.
6 *
7 * Author: Anan Sun <anan.sun@mediatek.com>
8 * Author: Yong Wu <yong.wu@mediatek.com>
9 */
10#ifndef _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
11#define _DT_BINDINGS_MEMORY_MT8186_LARB_PORT_H_
12
13#include <dt-bindings/memory/mtk-memory-port.h>
14
15/*
16 * MM IOMMU supports 16GB dma address. We separate it to four ranges:
17 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
18 * locate in anyone region. BUT:
19 * a) Make sure all the ports inside a larb are in one range.
20 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
21 *
22 * This is the suggested mapping in this SoC:
23 *
24 * modules    dma-address-region	larbs-ports
25 * disp         0 ~ 4G                  larb0/1/2
26 * vcodec      4G ~ 8G                  larb4/7
27 * cam/mdp     8G ~ 12G                 the other larbs.
28 * N/A         12G ~ 16G
29 * CCU0   0x24000_0000 ~ 0x243ff_ffff   larb13: port 9/10
30 * CCU1   0x24400_0000 ~ 0x247ff_ffff   larb14: port 4/5
31 */
32
33/* MM IOMMU ports */
34/* LARB 0 -- MMSYS */
35#define IOMMU_PORT_L0_DISP_POSTMASK0	MTK_M4U_ID(0, 0)
36#define IOMMU_PORT_L0_REVERSED		MTK_M4U_ID(0, 1)
37#define IOMMU_PORT_L0_OVL_RDMA0		MTK_M4U_ID(0, 2)
38#define IOMMU_PORT_L0_DISP_FAKE0	MTK_M4U_ID(0, 3)
39
40/* LARB 1 -- MMSYS */
41#define IOMMU_PORT_L1_DISP_RDMA1	MTK_M4U_ID(1, 0)
42#define IOMMU_PORT_L1_OVL_2L_RDMA0	MTK_M4U_ID(1, 1)
43#define IOMMU_PORT_L1_DISP_RDMA0	MTK_M4U_ID(1, 2)
44#define IOMMU_PORT_L1_DISP_WDMA0	MTK_M4U_ID(1, 3)
45#define IOMMU_PORT_L1_DISP_FAKE1	MTK_M4U_ID(1, 4)
46
47/* LARB 2 -- MMSYS */
48#define IOMMU_PORT_L2_MDP_RDMA0		MTK_M4U_ID(2, 0)
49#define IOMMU_PORT_L2_MDP_RDMA1		MTK_M4U_ID(2, 1)
50#define IOMMU_PORT_L2_MDP_WROT0		MTK_M4U_ID(2, 2)
51#define IOMMU_PORT_L2_MDP_WROT1		MTK_M4U_ID(2, 3)
52#define IOMMU_PORT_L2_DISP_FAKE0	MTK_M4U_ID(2, 4)
53
54/* LARB 4 -- VDEC */
55#define IOMMU_PORT_L4_HW_VDEC_MC_EXT		MTK_M4U_ID(4, 0)
56#define IOMMU_PORT_L4_HW_VDEC_UFO_EXT		MTK_M4U_ID(4, 1)
57#define IOMMU_PORT_L4_HW_VDEC_PP_EXT		MTK_M4U_ID(4, 2)
58#define IOMMU_PORT_L4_HW_VDEC_PRED_RD_EXT	MTK_M4U_ID(4, 3)
59#define IOMMU_PORT_L4_HW_VDEC_PRED_WR_EXT	MTK_M4U_ID(4, 4)
60#define IOMMU_PORT_L4_HW_VDEC_PPWRAP_EXT	MTK_M4U_ID(4, 5)
61#define IOMMU_PORT_L4_HW_VDEC_TILE_EXT		MTK_M4U_ID(4, 6)
62#define IOMMU_PORT_L4_HW_VDEC_VLD_EXT		MTK_M4U_ID(4, 7)
63#define IOMMU_PORT_L4_HW_VDEC_VLD2_EXT		MTK_M4U_ID(4, 8)
64#define IOMMU_PORT_L4_HW_VDEC_AVC_MV_EXT	MTK_M4U_ID(4, 9)
65#define IOMMU_PORT_L4_HW_VDEC_UFO_ENC_EXT	MTK_M4U_ID(4, 10)
66#define IOMMU_PORT_L4_HW_VDEC_RG_CTRL_DMA_EXT	MTK_M4U_ID(4, 11)
67#define IOMMU_PORT_L4_HW_MINI_MDP_R0_EXT	MTK_M4U_ID(4, 12)
68#define IOMMU_PORT_L4_HW_MINI_MDP_W0_EXT	MTK_M4U_ID(4, 13)
69
70/* LARB 7 -- VENC */
71#define IOMMU_PORT_L7_VENC_RCPU		MTK_M4U_ID(7, 0)
72#define IOMMU_PORT_L7_VENC_REC		MTK_M4U_ID(7, 1)
73#define IOMMU_PORT_L7_VENC_BSDMA	MTK_M4U_ID(7, 2)
74#define IOMMU_PORT_L7_VENC_SV_COMV	MTK_M4U_ID(7, 3)
75#define IOMMU_PORT_L7_VENC_RD_COMV	MTK_M4U_ID(7, 4)
76#define IOMMU_PORT_L7_VENC_CUR_LUMA	MTK_M4U_ID(7, 5)
77#define IOMMU_PORT_L7_VENC_CUR_CHROMA	MTK_M4U_ID(7, 6)
78#define IOMMU_PORT_L7_VENC_REF_LUMA	MTK_M4U_ID(7, 7)
79#define IOMMU_PORT_L7_VENC_REF_CHROMA	MTK_M4U_ID(7, 8)
80#define IOMMU_PORT_L7_JPGENC_Y_RDMA	MTK_M4U_ID(7, 9)
81#define IOMMU_PORT_L7_JPGENC_C_RDMA	MTK_M4U_ID(7, 10)
82#define IOMMU_PORT_L7_JPGENC_Q_TABLE	MTK_M4U_ID(7, 11)
83#define IOMMU_PORT_L7_JPGENC_BSDMA	MTK_M4U_ID(7, 12)
84
85/* LARB 8 -- WPE */
86#define IOMMU_PORT_L8_WPE_RDMA_0	MTK_M4U_ID(8, 0)
87#define IOMMU_PORT_L8_WPE_RDMA_1	MTK_M4U_ID(8, 1)
88#define IOMMU_PORT_L8_WPE_WDMA_0	MTK_M4U_ID(8, 2)
89
90/* LARB 9 -- IMG-1 */
91#define IOMMU_PORT_L9_IMG_IMGI_D1	MTK_M4U_ID(9, 0)
92#define IOMMU_PORT_L9_IMG_IMGBI_D1	MTK_M4U_ID(9, 1)
93#define IOMMU_PORT_L9_IMG_DMGI_D1	MTK_M4U_ID(9, 2)
94#define IOMMU_PORT_L9_IMG_DEPI_D1	MTK_M4U_ID(9, 3)
95#define IOMMU_PORT_L9_IMG_LCE_D1	MTK_M4U_ID(9, 4)
96#define IOMMU_PORT_L9_IMG_SMTI_D1	MTK_M4U_ID(9, 5)
97#define IOMMU_PORT_L9_IMG_SMTO_D2	MTK_M4U_ID(9, 6)
98#define IOMMU_PORT_L9_IMG_SMTO_D1	MTK_M4U_ID(9, 7)
99#define IOMMU_PORT_L9_IMG_CRZO_D1	MTK_M4U_ID(9, 8)
100#define IOMMU_PORT_L9_IMG_IMG3O_D1	MTK_M4U_ID(9, 9)
101#define IOMMU_PORT_L9_IMG_VIPI_D1	MTK_M4U_ID(9, 10)
102#define IOMMU_PORT_L9_IMG_SMTI_D5	MTK_M4U_ID(9, 11)
103#define IOMMU_PORT_L9_IMG_TIMGO_D1	MTK_M4U_ID(9, 12)
104#define IOMMU_PORT_L9_IMG_UFBC_W0	MTK_M4U_ID(9, 13)
105#define IOMMU_PORT_L9_IMG_UFBC_R0	MTK_M4U_ID(9, 14)
106#define IOMMU_PORT_L9_IMG_WPE_RDMA1	MTK_M4U_ID(9, 15)
107#define IOMMU_PORT_L9_IMG_WPE_RDMA0	MTK_M4U_ID(9, 16)
108#define IOMMU_PORT_L9_IMG_WPE_WDMA	MTK_M4U_ID(9, 17)
109#define IOMMU_PORT_L9_IMG_MFB_RDMA0	MTK_M4U_ID(9, 18)
110#define IOMMU_PORT_L9_IMG_MFB_RDMA1	MTK_M4U_ID(9, 19)
111#define IOMMU_PORT_L9_IMG_MFB_RDMA2	MTK_M4U_ID(9, 20)
112#define IOMMU_PORT_L9_IMG_MFB_RDMA3	MTK_M4U_ID(9, 21)
113#define IOMMU_PORT_L9_IMG_MFB_RDMA4	MTK_M4U_ID(9, 22)
114#define IOMMU_PORT_L9_IMG_MFB_RDMA5	MTK_M4U_ID(9, 23)
115#define IOMMU_PORT_L9_IMG_MFB_WDMA0	MTK_M4U_ID(9, 24)
116#define IOMMU_PORT_L9_IMG_MFB_WDMA1	MTK_M4U_ID(9, 25)
117#define IOMMU_PORT_L9_IMG_RESERVE6	MTK_M4U_ID(9, 26)
118#define IOMMU_PORT_L9_IMG_RESERVE7	MTK_M4U_ID(9, 27)
119#define IOMMU_PORT_L9_IMG_RESERVE8	MTK_M4U_ID(9, 28)
120
121/* LARB 11 -- IMG-2 */
122#define IOMMU_PORT_L11_IMG_IMGI_D1	MTK_M4U_ID(11, 0)
123#define IOMMU_PORT_L11_IMG_IMGBI_D1	MTK_M4U_ID(11, 1)
124#define IOMMU_PORT_L11_IMG_DMGI_D1	MTK_M4U_ID(11, 2)
125#define IOMMU_PORT_L11_IMG_DEPI_D1	MTK_M4U_ID(11, 3)
126#define IOMMU_PORT_L11_IMG_LCE_D1	MTK_M4U_ID(11, 4)
127#define IOMMU_PORT_L11_IMG_SMTI_D1	MTK_M4U_ID(11, 5)
128#define IOMMU_PORT_L11_IMG_SMTO_D2	MTK_M4U_ID(11, 6)
129#define IOMMU_PORT_L11_IMG_SMTO_D1	MTK_M4U_ID(11, 7)
130#define IOMMU_PORT_L11_IMG_CRZO_D1	MTK_M4U_ID(11, 8)
131#define IOMMU_PORT_L11_IMG_IMG3O_D1	MTK_M4U_ID(11, 9)
132#define IOMMU_PORT_L11_IMG_VIPI_D1	MTK_M4U_ID(11, 10)
133#define IOMMU_PORT_L11_IMG_SMTI_D5	MTK_M4U_ID(11, 11)
134#define IOMMU_PORT_L11_IMG_TIMGO_D1	MTK_M4U_ID(11, 12)
135#define IOMMU_PORT_L11_IMG_UFBC_W0	MTK_M4U_ID(11, 13)
136#define IOMMU_PORT_L11_IMG_UFBC_R0	MTK_M4U_ID(11, 14)
137#define IOMMU_PORT_L11_IMG_WPE_RDMA1	MTK_M4U_ID(11, 15)
138#define IOMMU_PORT_L11_IMG_WPE_RDMA0	MTK_M4U_ID(11, 16)
139#define IOMMU_PORT_L11_IMG_WPE_WDMA	MTK_M4U_ID(11, 17)
140#define IOMMU_PORT_L11_IMG_MFB_RDMA0	MTK_M4U_ID(11, 18)
141#define IOMMU_PORT_L11_IMG_MFB_RDMA1	MTK_M4U_ID(11, 19)
142#define IOMMU_PORT_L11_IMG_MFB_RDMA2	MTK_M4U_ID(11, 20)
143#define IOMMU_PORT_L11_IMG_MFB_RDMA3	MTK_M4U_ID(11, 21)
144#define IOMMU_PORT_L11_IMG_MFB_RDMA4	MTK_M4U_ID(11, 22)
145#define IOMMU_PORT_L11_IMG_MFB_RDMA5	MTK_M4U_ID(11, 23)
146#define IOMMU_PORT_L11_IMG_MFB_WDMA0	MTK_M4U_ID(11, 24)
147#define IOMMU_PORT_L11_IMG_MFB_WDMA1	MTK_M4U_ID(11, 25)
148#define IOMMU_PORT_L11_IMG_RESERVE6	MTK_M4U_ID(11, 26)
149#define IOMMU_PORT_L11_IMG_RESERVE7	MTK_M4U_ID(11, 27)
150#define IOMMU_PORT_L11_IMG_RESERVE8	MTK_M4U_ID(11, 28)
151
152/* LARB 13 -- CAM */
153#define IOMMU_PORT_L13_CAM_MRAWI	MTK_M4U_ID(13, 0)
154#define IOMMU_PORT_L13_CAM_MRAWO_0	MTK_M4U_ID(13, 1)
155#define IOMMU_PORT_L13_CAM_MRAWO_1	MTK_M4U_ID(13, 2)
156#define IOMMU_PORT_L13_CAM_CAMSV_4	MTK_M4U_ID(13, 6)
157#define IOMMU_PORT_L13_CAM_CAMSV_5	MTK_M4U_ID(13, 7)
158#define IOMMU_PORT_L13_CAM_CAMSV_6	MTK_M4U_ID(13, 8)
159#define IOMMU_PORT_L13_CAM_CCUI		MTK_M4U_ID(13, 9)
160#define IOMMU_PORT_L13_CAM_CCUO		MTK_M4U_ID(13, 10)
161#define IOMMU_PORT_L13_CAM_FAKE		MTK_M4U_ID(13, 11)
162
163/* LARB 14 -- CAM */
164#define IOMMU_PORT_L14_CAM_CCUI		MTK_M4U_ID(14, 4)
165#define IOMMU_PORT_L14_CAM_CCUO		MTK_M4U_ID(14, 5)
166
167/* LARB 16 -- RAW-A */
168#define IOMMU_PORT_L16_CAM_IMGO_R1_A	MTK_M4U_ID(16, 0)
169#define IOMMU_PORT_L16_CAM_RRZO_R1_A	MTK_M4U_ID(16, 1)
170#define IOMMU_PORT_L16_CAM_CQI_R1_A	MTK_M4U_ID(16, 2)
171#define IOMMU_PORT_L16_CAM_BPCI_R1_A	MTK_M4U_ID(16, 3)
172#define IOMMU_PORT_L16_CAM_YUVO_R1_A	MTK_M4U_ID(16, 4)
173#define IOMMU_PORT_L16_CAM_UFDI_R2_A	MTK_M4U_ID(16, 5)
174#define IOMMU_PORT_L16_CAM_RAWI_R2_A	MTK_M4U_ID(16, 6)
175#define IOMMU_PORT_L16_CAM_RAWI_R3_A	MTK_M4U_ID(16, 7)
176#define IOMMU_PORT_L16_CAM_AAO_R1_A	MTK_M4U_ID(16, 8)
177#define IOMMU_PORT_L16_CAM_AFO_R1_A	MTK_M4U_ID(16, 9)
178#define IOMMU_PORT_L16_CAM_FLKO_R1_A	MTK_M4U_ID(16, 10)
179#define IOMMU_PORT_L16_CAM_LCESO_R1_A	MTK_M4U_ID(16, 11)
180#define IOMMU_PORT_L16_CAM_CRZO_R1_A	MTK_M4U_ID(16, 12)
181#define IOMMU_PORT_L16_CAM_LTMSO_R1_A	MTK_M4U_ID(16, 13)
182#define IOMMU_PORT_L16_CAM_RSSO_R1_A	MTK_M4U_ID(16, 14)
183#define IOMMU_PORT_L16_CAM_AAHO_R1_A	MTK_M4U_ID(16, 15)
184#define IOMMU_PORT_L16_CAM_LSCI_R1_A	MTK_M4U_ID(16, 16)
185
186/* LARB 17 -- RAW-B */
187#define IOMMU_PORT_L17_CAM_IMGO_R1_B	MTK_M4U_ID(17, 0)
188#define IOMMU_PORT_L17_CAM_RRZO_R1_B	MTK_M4U_ID(17, 1)
189#define IOMMU_PORT_L17_CAM_CQI_R1_B	MTK_M4U_ID(17, 2)
190#define IOMMU_PORT_L17_CAM_BPCI_R1_B	MTK_M4U_ID(17, 3)
191#define IOMMU_PORT_L17_CAM_YUVO_R1_B	MTK_M4U_ID(17, 4)
192#define IOMMU_PORT_L17_CAM_UFDI_R2_B	MTK_M4U_ID(17, 5)
193#define IOMMU_PORT_L17_CAM_RAWI_R2_B	MTK_M4U_ID(17, 6)
194#define IOMMU_PORT_L17_CAM_RAWI_R3_B	MTK_M4U_ID(17, 7)
195#define IOMMU_PORT_L17_CAM_AAO_R1_B	MTK_M4U_ID(17, 8)
196#define IOMMU_PORT_L17_CAM_AFO_R1_B	MTK_M4U_ID(17, 9)
197#define IOMMU_PORT_L17_CAM_FLKO_R1_B	MTK_M4U_ID(17, 10)
198#define IOMMU_PORT_L17_CAM_LCESO_R1_B	MTK_M4U_ID(17, 11)
199#define IOMMU_PORT_L17_CAM_CRZO_R1_B	MTK_M4U_ID(17, 12)
200#define IOMMU_PORT_L17_CAM_LTMSO_R1_B	MTK_M4U_ID(17, 13)
201#define IOMMU_PORT_L17_CAM_RSSO_R1_B	MTK_M4U_ID(17, 14)
202#define IOMMU_PORT_L17_CAM_AAHO_R1_B	MTK_M4U_ID(17, 15)
203#define IOMMU_PORT_L17_CAM_LSCI_R1_B	MTK_M4U_ID(17, 16)
204
205/* LARB 19 -- IPE */
206#define IOMMU_PORT_L19_IPE_DVS_RDMA	MTK_M4U_ID(19, 0)
207#define IOMMU_PORT_L19_IPE_DVS_WDMA	MTK_M4U_ID(19, 1)
208#define IOMMU_PORT_L19_IPE_DVP_RDMA	MTK_M4U_ID(19, 2)
209#define IOMMU_PORT_L19_IPE_DVP_WDMA	MTK_M4U_ID(19, 3)
210
211/* LARB 20 -- IPE */
212#define IOMMU_PORT_L20_IPE_FDVT_RDA	MTK_M4U_ID(20, 0)
213#define IOMMU_PORT_L20_IPE_FDVT_RDB	MTK_M4U_ID(20, 1)
214#define IOMMU_PORT_L20_IPE_FDVT_WRA	MTK_M4U_ID(20, 2)
215#define IOMMU_PORT_L20_IPE_FDVT_WRB	MTK_M4U_ID(20, 3)
216#define IOMMU_PORT_L20_IPE_RSC_RDMA0	MTK_M4U_ID(20, 4)
217#define IOMMU_PORT_L20_IPE_RSC_WDMA	MTK_M4U_ID(20, 5)
218
219#endif
220