1/* $NetBSD: mt8195-memory-port.h,v 1.1.1.1 2026/01/18 05:21:48 skrll Exp $ */ 2 3/* SPDX-License-Identifier: GPL-2.0-only */ 4/* 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Yong Wu <yong.wu@mediatek.com> 7 */ 8#ifndef _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ 9#define _DT_BINDINGS_MEMORY_MT8195_LARB_PORT_H_ 10 11#include <dt-bindings/memory/mtk-memory-port.h> 12 13/* 14 * MM IOMMU supports 16GB dma address. We separate it to four ranges: 15 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters 16 * locate in anyone region. BUT: 17 * a) Make sure all the ports inside a larb are in one range. 18 * b) The iova of any master can NOT cross the 4G/8G/12G boundary. 19 * 20 * This is the suggested mapping in this SoC: 21 * 22 * modules dma-address-region larbs-ports 23 * disp 0 ~ 4G larb0/1/2/3 24 * vcodec 4G ~ 8G larb19/20/21/22/23/24 25 * cam/mdp 8G ~ 12G the other larbs. 26 * N/A 12G ~ 16G 27 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1 28 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3 29 * 30 * This SoC have two IOMMU HWs, this is the detailed connected information: 31 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28 32 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27 33 */ 34 35/* MM IOMMU ports */ 36/* larb0 */ 37#define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0) 38#define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1) 39#define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2) 40#define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3) 41#define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4) 42#define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5) 43 44/* larb1 */ 45#define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0) 46#define M4U_PORT_L1_DISP_WDMA0 MTK_M4U_ID(1, 1) 47#define M4U_PORT_L1_DISP_OVL0_RDMA0 MTK_M4U_ID(1, 2) 48#define M4U_PORT_L1_DISP_OVL0_RDMA1 MTK_M4U_ID(1, 3) 49#define M4U_PORT_L1_DISP_OVL0_HDR MTK_M4U_ID(1, 4) 50#define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5) 51 52/* larb2 */ 53#define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) 54#define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(2, 1) 55#define M4U_PORT_L2_MDP_RDMA4 MTK_M4U_ID(2, 2) 56#define M4U_PORT_L2_MDP_RDMA6 MTK_M4U_ID(2, 3) 57#define M4U_PORT_L2_DISP_FAKE1 MTK_M4U_ID(2, 4) 58 59/* larb3 */ 60#define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0) 61#define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(3, 1) 62#define M4U_PORT_L3_MDP_RDMA5 MTK_M4U_ID(3, 2) 63#define M4U_PORT_L3_MDP_RDMA7 MTK_M4U_ID(3, 3) 64#define M4U_PORT_L3_HDR_DS MTK_M4U_ID(3, 4) 65#define M4U_PORT_L3_HDR_ADL MTK_M4U_ID(3, 5) 66#define M4U_PORT_L3_DISP_FAKE1 MTK_M4U_ID(3, 6) 67 68/* larb4 */ 69#define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0) 70#define M4U_PORT_L4_MDP_FG MTK_M4U_ID(4, 1) 71#define M4U_PORT_L4_MDP_OVL MTK_M4U_ID(4, 2) 72#define M4U_PORT_L4_MDP_WROT MTK_M4U_ID(4, 3) 73#define M4U_PORT_L4_FAKE MTK_M4U_ID(4, 4) 74 75/* larb5 */ 76#define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0) 77#define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(5, 1) 78#define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(5, 2) 79#define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(5, 3) 80#define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(5, 4) 81#define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(5, 5) 82#define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(5, 6) 83#define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7) 84 85/* larb6 */ 86#define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0) 87#define M4U_PORT_L6_SVPP3_MDP_FG MTK_M4U_ID(6, 1) 88#define M4U_PORT_L6_SVPP3_MDP_WROT MTK_M4U_ID(6, 2) 89#define M4U_PORT_L6_FAKE MTK_M4U_ID(6, 3) 90 91/* larb7 */ 92#define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0) 93#define M4U_PORT_L7_IMG_WPE_RDMA1 MTK_M4U_ID(7, 1) 94#define M4U_PORT_L7_IMG_WPE_WDMA0 MTK_M4U_ID(7, 2) 95 96/* larb8 */ 97#define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0) 98#define M4U_PORT_L8_IMG_WPE_RDMA1 MTK_M4U_ID(8, 1) 99#define M4U_PORT_L8_IMG_WPE_WDMA0 MTK_M4U_ID(8, 2) 100 101/* larb9 */ 102#define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0) 103#define M4U_PORT_L9_IMG_IMGBI_T1_A MTK_M4U_ID(9, 1) 104#define M4U_PORT_L9_IMG_IMGCI_T1_A MTK_M4U_ID(9, 2) 105#define M4U_PORT_L9_IMG_SMTI_T1_A MTK_M4U_ID(9, 3) 106#define M4U_PORT_L9_IMG_TNCSTI_T1_A MTK_M4U_ID(9, 4) 107#define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5) 108#define M4U_PORT_L9_IMG_YUVO_T1_A MTK_M4U_ID(9, 6) 109#define M4U_PORT_L9_IMG_TIMGO_T1_A MTK_M4U_ID(9, 7) 110#define M4U_PORT_L9_IMG_YUVO_T2_A MTK_M4U_ID(9, 8) 111#define M4U_PORT_L9_IMG_IMGI_T1_B MTK_M4U_ID(9, 9) 112#define M4U_PORT_L9_IMG_IMGBI_T1_B MTK_M4U_ID(9, 10) 113#define M4U_PORT_L9_IMG_IMGCI_T1_B MTK_M4U_ID(9, 11) 114#define M4U_PORT_L9_IMG_YUVO_T5_A MTK_M4U_ID(9, 12) 115#define M4U_PORT_L9_IMG_SMTI_T1_B MTK_M4U_ID(9, 13) 116#define M4U_PORT_L9_IMG_TNCSO_T1_A MTK_M4U_ID(9, 14) 117#define M4U_PORT_L9_IMG_SMTO_T1_A MTK_M4U_ID(9, 15) 118#define M4U_PORT_L9_IMG_TNCSTO_T1_A MTK_M4U_ID(9, 16) 119#define M4U_PORT_L9_IMG_YUVO_T2_B MTK_M4U_ID(9, 17) 120#define M4U_PORT_L9_IMG_YUVO_T5_B MTK_M4U_ID(9, 18) 121#define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19) 122 123/* larb10 */ 124#define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0) 125#define M4U_PORT_L10_IMG_IMGCI_D1_A MTK_M4U_ID(10, 1) 126#define M4U_PORT_L10_IMG_DEPI_D1_A MTK_M4U_ID(10, 2) 127#define M4U_PORT_L10_IMG_DMGI_D1_A MTK_M4U_ID(10, 3) 128#define M4U_PORT_L10_IMG_VIPI_D1_A MTK_M4U_ID(10, 4) 129#define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5) 130#define M4U_PORT_L10_IMG_RECI_D1_A MTK_M4U_ID(10, 6) 131#define M4U_PORT_L10_IMG_SMTI_D1_A MTK_M4U_ID(10, 7) 132#define M4U_PORT_L10_IMG_SMTI_D6_A MTK_M4U_ID(10, 8) 133#define M4U_PORT_L10_IMG_PIMGI_P1_A MTK_M4U_ID(10, 9) 134#define M4U_PORT_L10_IMG_PIMGBI_P1_A MTK_M4U_ID(10, 10) 135#define M4U_PORT_L10_IMG_PIMGCI_P1_A MTK_M4U_ID(10, 11) 136#define M4U_PORT_L10_IMG_PIMGI_P1_B MTK_M4U_ID(10, 12) 137#define M4U_PORT_L10_IMG_PIMGBI_P1_B MTK_M4U_ID(10, 13) 138#define M4U_PORT_L10_IMG_PIMGCI_P1_B MTK_M4U_ID(10, 14) 139#define M4U_PORT_L10_IMG_IMG3O_D1_A MTK_M4U_ID(10, 15) 140#define M4U_PORT_L10_IMG_IMG4O_D1_A MTK_M4U_ID(10, 16) 141#define M4U_PORT_L10_IMG_IMG3CO_D1_A MTK_M4U_ID(10, 17) 142#define M4U_PORT_L10_IMG_FEO_D1_A MTK_M4U_ID(10, 18) 143#define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19) 144#define M4U_PORT_L10_IMG_TNRWO_D1_A MTK_M4U_ID(10, 20) 145#define M4U_PORT_L10_IMG_SMTO_D1_A MTK_M4U_ID(10, 21) 146#define M4U_PORT_L10_IMG_WROT_P1_A MTK_M4U_ID(10, 22) 147#define M4U_PORT_L10_IMG_WROT_P1_B MTK_M4U_ID(10, 23) 148 149/* larb11 */ 150#define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0) 151#define M4U_PORT_L11_IMG_WPE_EIS_RDMA1_A MTK_M4U_ID(11, 1) 152#define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A MTK_M4U_ID(11, 2) 153#define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A MTK_M4U_ID(11, 3) 154#define M4U_PORT_L11_IMG_WPE_TNR_RDMA1_A MTK_M4U_ID(11, 4) 155#define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5) 156#define M4U_PORT_L11_IMG_WPE_EIS_CQ0_A MTK_M4U_ID(11, 6) 157#define M4U_PORT_L11_IMG_WPE_EIS_CQ1_A MTK_M4U_ID(11, 7) 158#define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A MTK_M4U_ID(11, 8) 159#define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A MTK_M4U_ID(11, 9) 160 161/* larb12 */ 162#define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0) 163#define M4U_PORT_L12_IMG_FDVT_RDB MTK_M4U_ID(12, 1) 164#define M4U_PORT_L12_IMG_FDVT_WRA MTK_M4U_ID(12, 2) 165#define M4U_PORT_L12_IMG_FDVT_WRB MTK_M4U_ID(12, 3) 166#define M4U_PORT_L12_IMG_ME_RDMA MTK_M4U_ID(12, 4) 167#define M4U_PORT_L12_IMG_ME_WDMA MTK_M4U_ID(12, 5) 168#define M4U_PORT_L12_IMG_DVS_RDMA MTK_M4U_ID(12, 6) 169#define M4U_PORT_L12_IMG_DVS_WDMA MTK_M4U_ID(12, 7) 170#define M4U_PORT_L12_IMG_DVP_RDMA MTK_M4U_ID(12, 8) 171#define M4U_PORT_L12_IMG_DVP_WDMA MTK_M4U_ID(12, 9) 172 173/* larb13 */ 174#define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0) 175#define M4U_PORT_L13_CAM_CAMSV_CQI_E2 MTK_M4U_ID(13, 1) 176#define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0 MTK_M4U_ID(13, 2) 177#define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0 MTK_M4U_ID(13, 3) 178#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(13, 4) 179#define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(13, 5) 180#define M4U_PORT_L13_CAM_GCAMSV_A_UFEO_0 MTK_M4U_ID(13, 6) 181#define M4U_PORT_L13_CAM_GCAMSV_B_UFEO_0 MTK_M4U_ID(13, 7) 182#define M4U_PORT_L13_CAM_PDAI_0 MTK_M4U_ID(13, 8) 183#define M4U_PORT_L13_CAM_FAKE MTK_M4U_ID(13, 9) 184 185/* larb14 */ 186#define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0) 187#define M4U_PORT_L14_CAM_SCAMSV_A_IMGO_1 MTK_M4U_ID(14, 1) 188#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0 MTK_M4U_ID(14, 2) 189#define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(14, 3) 190#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_0 MTK_M4U_ID(14, 4) 191#define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1 MTK_M4U_ID(14, 5) 192#define M4U_PORT_L14_CAM_IPUI MTK_M4U_ID(14, 6) 193#define M4U_PORT_L14_CAM_IPU2I MTK_M4U_ID(14, 7) 194#define M4U_PORT_L14_CAM_IPUO MTK_M4U_ID(14, 8) 195#define M4U_PORT_L14_CAM_IPU2O MTK_M4U_ID(14, 9) 196#define M4U_PORT_L14_CAM_IPU3O MTK_M4U_ID(14, 10) 197#define M4U_PORT_L14_CAM_GCAMSV_A_UFEO_1 MTK_M4U_ID(14, 11) 198#define M4U_PORT_L14_CAM_GCAMSV_B_UFEO_1 MTK_M4U_ID(14, 12) 199#define M4U_PORT_L14_CAM_PDAI_1 MTK_M4U_ID(14, 13) 200#define M4U_PORT_L14_CAM_PDAO MTK_M4U_ID(14, 14) 201 202/* larb15: null */ 203 204/* larb16 */ 205#define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0) 206#define M4U_PORT_L16_CAM_CQI_R1 MTK_M4U_ID(16, 1) 207#define M4U_PORT_L16_CAM_CQI_R2 MTK_M4U_ID(16, 2) 208#define M4U_PORT_L16_CAM_BPCI_R1 MTK_M4U_ID(16, 3) 209#define M4U_PORT_L16_CAM_LSCI_R1 MTK_M4U_ID(16, 4) 210#define M4U_PORT_L16_CAM_RAWI_R2 MTK_M4U_ID(16, 5) 211#define M4U_PORT_L16_CAM_RAWI_R3 MTK_M4U_ID(16, 6) 212#define M4U_PORT_L16_CAM_UFDI_R2 MTK_M4U_ID(16, 7) 213#define M4U_PORT_L16_CAM_UFDI_R3 MTK_M4U_ID(16, 8) 214#define M4U_PORT_L16_CAM_RAWI_R4 MTK_M4U_ID(16, 9) 215#define M4U_PORT_L16_CAM_RAWI_R5 MTK_M4U_ID(16, 10) 216#define M4U_PORT_L16_CAM_AAI_R1 MTK_M4U_ID(16, 11) 217#define M4U_PORT_L16_CAM_FHO_R1 MTK_M4U_ID(16, 12) 218#define M4U_PORT_L16_CAM_AAO_R1 MTK_M4U_ID(16, 13) 219#define M4U_PORT_L16_CAM_TSFSO_R1 MTK_M4U_ID(16, 14) 220#define M4U_PORT_L16_CAM_FLKO_R1 MTK_M4U_ID(16, 15) 221 222/* larb17 */ 223#define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0) 224#define M4U_PORT_L17_CAM_YUVO_R3 MTK_M4U_ID(17, 1) 225#define M4U_PORT_L17_CAM_YUVCO_R1 MTK_M4U_ID(17, 2) 226#define M4U_PORT_L17_CAM_YUVO_R2 MTK_M4U_ID(17, 3) 227#define M4U_PORT_L17_CAM_RZH1N2TO_R1 MTK_M4U_ID(17, 4) 228#define M4U_PORT_L17_CAM_DRZS4NO_R1 MTK_M4U_ID(17, 5) 229#define M4U_PORT_L17_CAM_TNCSO_R1 MTK_M4U_ID(17, 6) 230 231/* larb18 */ 232#define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0) 233#define M4U_PORT_L18_CAM_CCUO MTK_M4U_ID(18, 1) 234#define M4U_PORT_L18_CAM_CCUI2 MTK_M4U_ID(18, 2) 235#define M4U_PORT_L18_CAM_CCUO2 MTK_M4U_ID(18, 3) 236 237/* larb19 */ 238#define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0) 239#define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1) 240#define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2) 241#define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3) 242#define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4) 243#define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5) 244#define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6) 245#define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7) 246#define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8) 247#define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9) 248#define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10) 249#define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11) 250#define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12) 251#define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13) 252#define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14) 253#define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15) 254#define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16) 255#define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17) 256#define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18) 257#define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19) 258#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20) 259#define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21) 260#define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22) 261#define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23) 262#define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24) 263#define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25) 264#define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26) 265 266/* larb20 */ 267#define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0) 268#define M4U_PORT_L20_VENC_REC MTK_M4U_ID(20, 1) 269#define M4U_PORT_L20_VENC_BSDMA MTK_M4U_ID(20, 2) 270#define M4U_PORT_L20_VENC_SV_COMV MTK_M4U_ID(20, 3) 271#define M4U_PORT_L20_VENC_RD_COMV MTK_M4U_ID(20, 4) 272#define M4U_PORT_L20_VENC_NBM_RDMA MTK_M4U_ID(20, 5) 273#define M4U_PORT_L20_VENC_NBM_RDMA_LITE MTK_M4U_ID(20, 6) 274#define M4U_PORT_L20_JPGENC_Y_RDMA MTK_M4U_ID(20, 7) 275#define M4U_PORT_L20_JPGENC_C_RDMA MTK_M4U_ID(20, 8) 276#define M4U_PORT_L20_JPGENC_Q_TABLE MTK_M4U_ID(20, 9) 277#define M4U_PORT_L20_VENC_SUB_W_LUMA MTK_M4U_ID(20, 10) 278#define M4U_PORT_L20_VENC_FCS_NBM_RDMA MTK_M4U_ID(20, 11) 279#define M4U_PORT_L20_JPGENC_BSDMA MTK_M4U_ID(20, 12) 280#define M4U_PORT_L20_JPGDEC_WDMA0 MTK_M4U_ID(20, 13) 281#define M4U_PORT_L20_JPGDEC_BSDMA0 MTK_M4U_ID(20, 14) 282#define M4U_PORT_L20_VENC_NBM_WDMA MTK_M4U_ID(20, 15) 283#define M4U_PORT_L20_VENC_NBM_WDMA_LITE MTK_M4U_ID(20, 16) 284#define M4U_PORT_L20_VENC_FCS_NBM_WDMA MTK_M4U_ID(20, 17) 285#define M4U_PORT_L20_JPGDEC_WDMA1 MTK_M4U_ID(20, 18) 286#define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19) 287#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(20, 20) 288#define M4U_PORT_L20_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(20, 21) 289#define M4U_PORT_L20_VENC_CUR_LUMA MTK_M4U_ID(20, 22) 290#define M4U_PORT_L20_VENC_CUR_CHROMA MTK_M4U_ID(20, 23) 291#define M4U_PORT_L20_VENC_REF_LUMA MTK_M4U_ID(20, 24) 292#define M4U_PORT_L20_VENC_REF_CHROMA MTK_M4U_ID(20, 25) 293#define M4U_PORT_L20_VENC_SUB_R_CHROMA MTK_M4U_ID(20, 26) 294 295/* larb21 */ 296#define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0) 297#define M4U_PORT_L21_VDEC_UFO_EXT MTK_M4U_ID(21, 1) 298#define M4U_PORT_L21_VDEC_PP_EXT MTK_M4U_ID(21, 2) 299#define M4U_PORT_L21_VDEC_PRED_RD_EXT MTK_M4U_ID(21, 3) 300#define M4U_PORT_L21_VDEC_PRED_WR_EXT MTK_M4U_ID(21, 4) 301#define M4U_PORT_L21_VDEC_PPWRAP_EXT MTK_M4U_ID(21, 5) 302#define M4U_PORT_L21_VDEC_TILE_EXT MTK_M4U_ID(21, 6) 303#define M4U_PORT_L21_VDEC_VLD_EXT MTK_M4U_ID(21, 7) 304#define M4U_PORT_L21_VDEC_VLD2_EXT MTK_M4U_ID(21, 8) 305#define M4U_PORT_L21_VDEC_AVC_MV_EXT MTK_M4U_ID(21, 9) 306 307/* larb22 */ 308#define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0) 309#define M4U_PORT_L22_VDEC_UFO_EXT MTK_M4U_ID(22, 1) 310#define M4U_PORT_L22_VDEC_PP_EXT MTK_M4U_ID(22, 2) 311#define M4U_PORT_L22_VDEC_PRED_RD_EXT MTK_M4U_ID(22, 3) 312#define M4U_PORT_L22_VDEC_PRED_WR_EXT MTK_M4U_ID(22, 4) 313#define M4U_PORT_L22_VDEC_PPWRAP_EXT MTK_M4U_ID(22, 5) 314#define M4U_PORT_L22_VDEC_TILE_EXT MTK_M4U_ID(22, 6) 315#define M4U_PORT_L22_VDEC_VLD_EXT MTK_M4U_ID(22, 7) 316#define M4U_PORT_L22_VDEC_VLD2_EXT MTK_M4U_ID(22, 8) 317#define M4U_PORT_L22_VDEC_AVC_MV_EXT MTK_M4U_ID(22, 9) 318 319/* larb23 */ 320#define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0) 321#define M4U_PORT_L23_VDEC_RDMA_EXT MTK_M4U_ID(23, 1) 322 323/* larb24 */ 324#define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0) 325#define M4U_PORT_L24_VDEC_LAT0_VLD2_EXT MTK_M4U_ID(24, 1) 326#define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT MTK_M4U_ID(24, 2) 327#define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT MTK_M4U_ID(24, 3) 328#define M4U_PORT_L24_VDEC_LAT0_TILE_EXT MTK_M4U_ID(24, 4) 329#define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(24, 5) 330#define M4U_PORT_L24_VDEC_LAT1_VLD_EXT MTK_M4U_ID(24, 6) 331#define M4U_PORT_L24_VDEC_LAT1_VLD2_EXT MTK_M4U_ID(24, 7) 332#define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT MTK_M4U_ID(24, 8) 333#define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT MTK_M4U_ID(24, 9) 334#define M4U_PORT_L24_VDEC_LAT1_TILE_EXT MTK_M4U_ID(24, 10) 335#define M4U_PORT_L24_VDEC_LAT1_WDMA_EXT MTK_M4U_ID(24, 11) 336 337/* larb25 */ 338#define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0) 339#define M4U_PORT_L25_CAM_MRAW0_CQI_M1 MTK_M4U_ID(25, 1) 340#define M4U_PORT_L25_CAM_MRAW0_CQI_M2 MTK_M4U_ID(25, 2) 341#define M4U_PORT_L25_CAM_MRAW0_IMGO_M1 MTK_M4U_ID(25, 3) 342#define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1 MTK_M4U_ID(25, 4) 343#define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_ID(25, 5) 344#define M4U_PORT_L25_CAM_MRAW2_CQI_M1 MTK_M4U_ID(25, 6) 345#define M4U_PORT_L25_CAM_MRAW2_CQI_M2 MTK_M4U_ID(25, 7) 346#define M4U_PORT_L25_CAM_MRAW2_IMGO_M1 MTK_M4U_ID(25, 8) 347#define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1 MTK_M4U_ID(25, 9) 348#define M4U_PORT_L25_CAM_MRAW0_AFO_M1 MTK_M4U_ID(25, 10) 349#define M4U_PORT_L25_CAM_MRAW2_AFO_M1 MTK_M4U_ID(25, 11) 350 351/* larb26 */ 352#define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0) 353#define M4U_PORT_L26_CAM_MRAW1_CQI_M1 MTK_M4U_ID(26, 1) 354#define M4U_PORT_L26_CAM_MRAW1_CQI_M2 MTK_M4U_ID(26, 2) 355#define M4U_PORT_L26_CAM_MRAW1_IMGO_M1 MTK_M4U_ID(26, 3) 356#define M4U_PORT_L26_CAM_MRAW1_IMGBO_M1 MTK_M4U_ID(26, 4) 357#define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_ID(26, 5) 358#define M4U_PORT_L26_CAM_MRAW3_CQI_M1 MTK_M4U_ID(26, 6) 359#define M4U_PORT_L26_CAM_MRAW3_CQI_M2 MTK_M4U_ID(26, 7) 360#define M4U_PORT_L26_CAM_MRAW3_IMGO_M1 MTK_M4U_ID(26, 8) 361#define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1 MTK_M4U_ID(26, 9) 362#define M4U_PORT_L26_CAM_MRAW1_AFO_M1 MTK_M4U_ID(26, 10) 363#define M4U_PORT_L26_CAM_MRAW3_AFO_M1 MTK_M4U_ID(26, 11) 364 365/* larb27 */ 366#define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0) 367#define M4U_PORT_L27_CAM_CQI_R1 MTK_M4U_ID(27, 1) 368#define M4U_PORT_L27_CAM_CQI_R2 MTK_M4U_ID(27, 2) 369#define M4U_PORT_L27_CAM_BPCI_R1 MTK_M4U_ID(27, 3) 370#define M4U_PORT_L27_CAM_LSCI_R1 MTK_M4U_ID(27, 4) 371#define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5) 372#define M4U_PORT_L27_CAM_RAWI_R3 MTK_M4U_ID(27, 6) 373#define M4U_PORT_L27_CAM_UFDI_R2 MTK_M4U_ID(27, 7) 374#define M4U_PORT_L27_CAM_UFDI_R3 MTK_M4U_ID(27, 8) 375#define M4U_PORT_L27_CAM_RAWI_R4 MTK_M4U_ID(27, 9) 376#define M4U_PORT_L27_CAM_RAWI_R5 MTK_M4U_ID(27, 10) 377#define M4U_PORT_L27_CAM_AAI_R1 MTK_M4U_ID(27, 11) 378#define M4U_PORT_L27_CAM_FHO_R1 MTK_M4U_ID(27, 12) 379#define M4U_PORT_L27_CAM_AAO_R1 MTK_M4U_ID(27, 13) 380#define M4U_PORT_L27_CAM_TSFSO_R1 MTK_M4U_ID(27, 14) 381#define M4U_PORT_L27_CAM_FLKO_R1 MTK_M4U_ID(27, 15) 382 383/* larb28 */ 384#define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0) 385#define M4U_PORT_L28_CAM_YUVO_R3 MTK_M4U_ID(28, 1) 386#define M4U_PORT_L28_CAM_YUVCO_R1 MTK_M4U_ID(28, 2) 387#define M4U_PORT_L28_CAM_YUVO_R2 MTK_M4U_ID(28, 3) 388#define M4U_PORT_L28_CAM_RZH1N2TO_R1 MTK_M4U_ID(28, 4) 389#define M4U_PORT_L28_CAM_DRZS4NO_R1 MTK_M4U_ID(28, 5) 390#define M4U_PORT_L28_CAM_TNCSO_R1 MTK_M4U_ID(28, 6) 391 392/* Infra iommu ports */ 393/* PCIe1: read: BIT16; write BIT17. */ 394#define IOMMU_PORT_INFRA_PCIE1 MTK_IFAIOMMU_PERI_ID(16) 395/* PCIe0: read: BIT18; write BIT19. */ 396#define IOMMU_PORT_INFRA_PCIE0 MTK_IFAIOMMU_PERI_ID(18) 397#define IOMMU_PORT_INFRA_SSUSB_P3_R MTK_IFAIOMMU_PERI_ID(20) 398#define IOMMU_PORT_INFRA_SSUSB_P3_W MTK_IFAIOMMU_PERI_ID(21) 399#define IOMMU_PORT_INFRA_SSUSB_P2_R MTK_IFAIOMMU_PERI_ID(22) 400#define IOMMU_PORT_INFRA_SSUSB_P2_W MTK_IFAIOMMU_PERI_ID(23) 401#define IOMMU_PORT_INFRA_SSUSB_P1_1_R MTK_IFAIOMMU_PERI_ID(24) 402#define IOMMU_PORT_INFRA_SSUSB_P1_1_W MTK_IFAIOMMU_PERI_ID(25) 403#define IOMMU_PORT_INFRA_SSUSB_P1_0_R MTK_IFAIOMMU_PERI_ID(26) 404#define IOMMU_PORT_INFRA_SSUSB_P1_0_W MTK_IFAIOMMU_PERI_ID(27) 405#define IOMMU_PORT_INFRA_SSUSB2_R MTK_IFAIOMMU_PERI_ID(28) 406#define IOMMU_PORT_INFRA_SSUSB2_W MTK_IFAIOMMU_PERI_ID(29) 407#define IOMMU_PORT_INFRA_SSUSB_R MTK_IFAIOMMU_PERI_ID(30) 408#define IOMMU_PORT_INFRA_SSUSB_W MTK_IFAIOMMU_PERI_ID(31) 409 410#endif 411