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      1 /*	$NetBSD: tegra20-mc.h,v 1.1.1.2 2021/11/07 16:49:56 jmcneill Exp $	*/
      2 
      3 /* SPDX-License-Identifier: GPL-2.0 */
      4 #ifndef DT_BINDINGS_MEMORY_TEGRA20_MC_H
      5 #define DT_BINDINGS_MEMORY_TEGRA20_MC_H
      6 
      7 #define TEGRA20_MC_RESET_AVPC		0
      8 #define TEGRA20_MC_RESET_DC		1
      9 #define TEGRA20_MC_RESET_DCB		2
     10 #define TEGRA20_MC_RESET_EPP		3
     11 #define TEGRA20_MC_RESET_2D		4
     12 #define TEGRA20_MC_RESET_HC		5
     13 #define TEGRA20_MC_RESET_ISP		6
     14 #define TEGRA20_MC_RESET_MPCORE		7
     15 #define TEGRA20_MC_RESET_MPEA		8
     16 #define TEGRA20_MC_RESET_MPEB		9
     17 #define TEGRA20_MC_RESET_MPEC		10
     18 #define TEGRA20_MC_RESET_3D		11
     19 #define TEGRA20_MC_RESET_PPCS		12
     20 #define TEGRA20_MC_RESET_VDE		13
     21 #define TEGRA20_MC_RESET_VI		14
     22 
     23 #define TEGRA20_MC_DISPLAY0A		0
     24 #define TEGRA20_MC_DISPLAY0AB		1
     25 #define TEGRA20_MC_DISPLAY0B		2
     26 #define TEGRA20_MC_DISPLAY0BB		3
     27 #define TEGRA20_MC_DISPLAY0C		4
     28 #define TEGRA20_MC_DISPLAY0CB		5
     29 #define TEGRA20_MC_DISPLAY1B		6
     30 #define TEGRA20_MC_DISPLAY1BB		7
     31 #define TEGRA20_MC_EPPUP		8
     32 #define TEGRA20_MC_G2PR			9
     33 #define TEGRA20_MC_G2SR			10
     34 #define TEGRA20_MC_MPEUNIFBR		11
     35 #define TEGRA20_MC_VIRUV		12
     36 #define TEGRA20_MC_AVPCARM7R		13
     37 #define TEGRA20_MC_DISPLAYHC		14
     38 #define TEGRA20_MC_DISPLAYHCB		15
     39 #define TEGRA20_MC_FDCDRD		16
     40 #define TEGRA20_MC_G2DR			17
     41 #define TEGRA20_MC_HOST1XDMAR		18
     42 #define TEGRA20_MC_HOST1XR		19
     43 #define TEGRA20_MC_IDXSRD		20
     44 #define TEGRA20_MC_MPCORER		21
     45 #define TEGRA20_MC_MPE_IPRED		22
     46 #define TEGRA20_MC_MPEAMEMRD		23
     47 #define TEGRA20_MC_MPECSRD		24
     48 #define TEGRA20_MC_PPCSAHBDMAR		25
     49 #define TEGRA20_MC_PPCSAHBSLVR		26
     50 #define TEGRA20_MC_TEXSRD		27
     51 #define TEGRA20_MC_VDEBSEVR		28
     52 #define TEGRA20_MC_VDEMBER		29
     53 #define TEGRA20_MC_VDEMCER		30
     54 #define TEGRA20_MC_VDETPER		31
     55 #define TEGRA20_MC_EPPU			32
     56 #define TEGRA20_MC_EPPV			33
     57 #define TEGRA20_MC_EPPY			34
     58 #define TEGRA20_MC_MPEUNIFBW		35
     59 #define TEGRA20_MC_VIWSB		36
     60 #define TEGRA20_MC_VIWU			37
     61 #define TEGRA20_MC_VIWV			38
     62 #define TEGRA20_MC_VIWY			39
     63 #define TEGRA20_MC_G2DW			40
     64 #define TEGRA20_MC_AVPCARM7W		41
     65 #define TEGRA20_MC_FDCDWR		42
     66 #define TEGRA20_MC_HOST1XW		43
     67 #define TEGRA20_MC_ISPW			44
     68 #define TEGRA20_MC_MPCOREW		45
     69 #define TEGRA20_MC_MPECSWR		46
     70 #define TEGRA20_MC_PPCSAHBDMAW		47
     71 #define TEGRA20_MC_PPCSAHBSLVW		48
     72 #define TEGRA20_MC_VDEBSEVW		49
     73 #define TEGRA20_MC_VDEMBEW		50
     74 #define TEGRA20_MC_VDETPMW		51
     75 
     76 #endif
     77